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  4. Reconstruction-computation-quantization (RCQ): a paradigm for low bit width LDPC decoding
 
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Reconstruction-computation-quantization (RCQ): a paradigm for low bit width LDPC decoding

Publikationstyp
Journal Article
Date Issued
2022-02-07
Sprache
English
Author(s)
Wang, Linfang  
Terrill, Caleb  
Stark, Maximilian  orcid-logo
LI, Zongwang  
Chen, Sean  
Hulse, Chester  
Kuo, Calvin  
Wesel, Richard D.  
Bauch, Gerhard  
Pitchumani, Rekha  
Institut
Nachrichtentechnik E-8  
TORE-URI
http://hdl.handle.net/11420/12590
Journal
IEEE transactions on communications  
Volume
70
Issue
4
Start Page
2213
End Page
2226
Citation
IEEE Transactions on Communications 70 (4): 2213-2226 (2022-04-01)
Publisher DOI
10.1109/TCOMM.2022.3149913
Scopus ID
2-s2.0-85124713976
Publisher
IEEE
This paper uses the reconstruction-computation-quantization (RCQ)paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution. Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding Min Sum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ, an extension of RCQ decoding for layered architectures. Layer-specific RCQ uses layer-specific message representations to achieve the best possible FER performance. For layer-specific RCQ, this paper proposes using layered discrete density evolution featuring hierarchical dynamic quantization (HDQ) to design parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered Min Sum RCQ decoder with 3-bit messages achieves more than a 10% reduction in LUTs and routed nets and more than a 6% decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset Min Sum decoder.
Subjects
FPGA
Hardware efficiency
Layered decoding
LDPC decoder
Low bit width decoding
DDC Class
004: Informatik
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