Signal Integrity Assessment of External ESD Protection for Gbit/s Data Rates on Ceramic Test Fixture

Abstract

In order to reduce the strain of ESD events on the internal ESD protection of I/O buffers, external ESD protection is deployed in form of standalone chips soldered on the signal trace on the ceramic. These elements introduce parasitics which need to be minimized or compensated in order to limit the degradation of signal integrity. This paper investigates the signal integrity performance of a standalone ESD protection device for multi Gbit/s data rates including nonlinear junction capacitance due to the ESD protection diode. Good model to hardware correlation is demonstrated by comparing simulation results with measurements up to 40 GHz. The results show that the nonlinear junction capacitance can be approximated as linear for the investigated cases.