Please use this identifier to cite or link to this item:
https://doi.org/10.15480/882.2018
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ranjan, Rajeev | - |
dc.contributor.author | Mendoza Ponce, Pablo | - |
dc.contributor.author | Hellweg, Wolf Lukas | - |
dc.contributor.author | Kyrmanidis, Alexandros | - |
dc.contributor.author | Abu Saleh, Lait | - |
dc.contributor.author | Schroeder, Dietmar | - |
dc.contributor.author | Krautschneider, Wolfgang H. | - |
dc.date.accessioned | 2019-02-28T08:56:35Z | - |
dc.date.available | 2019-02-28T08:56:35Z | - |
dc.date.issued | 2017-04-27 | - |
dc.identifier.citation | Journal of Circuits, Systems and Computers 11 (26): 1750183 (2017) | de_DE |
dc.identifier.issn | 0218-1266 | de_DE |
dc.identifier.uri | http://hdl.handle.net/11420/2021 | - |
dc.description.abstract | This paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88ns to 4.99μs (200kOhm) to 204.8MOhm)) and other four having conductance ranging from 195ns to 190μs (5.2kOhm) to 5.12MOhm)). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350nm process. | en |
dc.language.iso | en | de_DE |
dc.publisher | World Scientific Publishing | de_DE |
dc.relation.ispartof | Journal of circuits, systems, and computers | de_DE |
dc.rights | CC BY 4.0 | de_DE |
dc.rights.uri | https://creativecommons.org/licenses/by/4.0/ | de_DE |
dc.subject | ASIC | de_DE |
dc.subject | emulator | de_DE |
dc.subject | CMOS | de_DE |
dc.subject | LTD | de_DE |
dc.subject | LTP | de_DE |
dc.subject | memristor | de_DE |
dc.subject | neuron | de_DE |
dc.subject | synaptic plasticity | de_DE |
dc.subject | pattern recognition | de_DE |
dc.subject.ddc | 570: Biowissenschaften, Biologie | de_DE |
dc.title | Integrated circuit with memristor emulator array and neuron circuits for biologically inspired neuromorphic pattern recognition | de_DE |
dc.type | Article | de_DE |
dc.identifier.urn | urn:nbn:de:gbv:830-882.026562 | - |
dc.identifier.doi | 10.15480/882.2018 | - |
dc.type.dini | article | - |
dc.subject.ddccode | 570 | - |
dcterms.DCMIType | Text | - |
tuhh.identifier.urn | urn:nbn:de:gbv:830-882.026562 | - |
tuhh.oai.show | true | de_DE |
tuhh.abstract.english | This paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88ns to 4.99μs (200kOhm) to 204.8MOhm)) and other four having conductance ranging from 195ns to 190μs (5.2kOhm) to 5.12MOhm)). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350nm process. | de_DE |
tuhh.publisher.doi | 10.1142/S0218126617501833 | - |
tuhh.publication.institute | Integrierte Schaltungen E-9 | de_DE |
tuhh.identifier.doi | 10.15480/882.2018 | - |
tuhh.type.opus | (wissenschaftlicher) Artikel | - |
tuhh.institute.german | Integrierte Schaltungen E-9 | de |
tuhh.institute.english | Integrierte Schaltungen E-9 | de_DE |
tuhh.gvk.hasppn | false | - |
openaire.rights | info:eu-repo/semantics/openAccess | de_DE |
dc.type.driver | article | - |
dc.rights.ccversion | 4.0 | de_DE |
dc.type.casrai | Journal Article | - |
tuhh.container.issue | 11 | de_DE |
tuhh.container.volume | 26 | de_DE |
tuhh.container.startpage | 1750183 | de_DE |
dc.relation.project | FOR 2093: Memristive Bauelemente für neuronale Systeme, Teilprojekt C2 "Neuronale Schaltungen" | de_DE |
dc.rights.nationallicense | false | de_DE |
dc.identifier.scopus | 2-s2.0-85020195902 | - |
local.status.inpress | false | de_DE |
local.funding.info | Deutsche Forschungsgemeinschaft (DFG) | de_DE |
datacite.resourceType | Journal Article | - |
datacite.resourceTypeGeneral | Text | - |
item.mappedtype | Article | - |
item.openairetype | Article | - |
item.languageiso639-1 | en | - |
item.grantfulltext | open | - |
item.cerifentitytype | Publications | - |
item.creatorOrcid | Ranjan, Rajeev | - |
item.creatorOrcid | Mendoza Ponce, Pablo | - |
item.creatorOrcid | Hellweg, Wolf Lukas | - |
item.creatorOrcid | Kyrmanidis, Alexandros | - |
item.creatorOrcid | Abu Saleh, Lait | - |
item.creatorOrcid | Schroeder, Dietmar | - |
item.creatorOrcid | Krautschneider, Wolfgang H. | - |
item.creatorGND | Ranjan, Rajeev | - |
item.creatorGND | Mendoza Ponce, Pablo | - |
item.creatorGND | Hellweg, Wolf Lukas | - |
item.creatorGND | Kyrmanidis, Alexandros | - |
item.creatorGND | Abu Saleh, Lait | - |
item.creatorGND | Schroeder, Dietmar | - |
item.creatorGND | Krautschneider, Wolfgang H. | - |
item.fulltext | With Fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
crisitem.project.funder | Deutsche Forschungsgemeinschaft (DFG) | - |
crisitem.project.funderid | 501100001659 | - |
crisitem.project.funderrorid | 018mejw64 | - |
crisitem.project.grantno | KR 3281/8-3 | - |
crisitem.author.dept | Integrierte Schaltungen E-9 | - |
crisitem.author.dept | Integrierte Schaltungen E-9 | - |
crisitem.author.dept | Integrierte Schaltungen E-9 | - |
crisitem.author.dept | Integrierte Schaltungen E-9 | - |
crisitem.author.dept | Integrierte Schaltungen E-9 | - |
crisitem.author.dept | Integrierte Schaltungen E-9 | - |
crisitem.author.dept | Integrierte Schaltungen E-9 | - |
crisitem.author.orcid | 0000-0003-1048-577X | - |
crisitem.author.orcid | 0000-0001-5891-3628 | - |
crisitem.author.orcid | 0000-0001-8629-4545 | - |
crisitem.author.parentorg | Studiendekanat Elektrotechnik, Informatik und Mathematik (E) | - |
crisitem.author.parentorg | Studiendekanat Elektrotechnik, Informatik und Mathematik (E) | - |
crisitem.author.parentorg | Studiendekanat Elektrotechnik, Informatik und Mathematik (E) | - |
crisitem.author.parentorg | Studiendekanat Elektrotechnik, Informatik und Mathematik (E) | - |
crisitem.author.parentorg | Studiendekanat Elektrotechnik, Informatik und Mathematik (E) | - |
crisitem.author.parentorg | Studiendekanat Elektrotechnik, Informatik und Mathematik (E) | - |
crisitem.author.parentorg | Studiendekanat Elektrotechnik, Informatik und Mathematik (E) | - |
Appears in Collections: | Publications with fulltext |
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