Please use this identifier to cite or link to this item: https://doi.org/10.15480/882.2018
DC FieldValueLanguage
dc.contributor.authorRanjan, Rajeev-
dc.contributor.authorMendoza Ponce, Pablo-
dc.contributor.authorHellweg, Wolf Lukas-
dc.contributor.authorKyrmanidis, Alexandros-
dc.contributor.authorAbu Saleh, Lait-
dc.contributor.authorSchroeder, Dietmar-
dc.contributor.authorKrautschneider, Wolfgang H.-
dc.date.accessioned2019-02-28T08:56:35Z-
dc.date.available2019-02-28T08:56:35Z-
dc.date.issued2017-04-27-
dc.identifier.citationJournal of Circuits, Systems and Computers 11 (26): 1750183 (2017)de_DE
dc.identifier.issn0218-1266de_DE
dc.identifier.urihttp://hdl.handle.net/11420/2021-
dc.description.abstractThis paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88ns to 4.99μs (200kOhm) to 204.8MOhm)) and other four having conductance ranging from 195ns to 190μs (5.2kOhm) to 5.12MOhm)). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350nm process.en
dc.language.isoende_DE
dc.publisherWorld Scientific Publishingde_DE
dc.relation.ispartofJournal of circuits, systems, and computersde_DE
dc.rightsCC BY 4.0de_DE
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/de_DE
dc.subjectASICde_DE
dc.subjectemulatorde_DE
dc.subjectCMOSde_DE
dc.subjectLTDde_DE
dc.subjectLTPde_DE
dc.subjectmemristorde_DE
dc.subjectneuronde_DE
dc.subjectsynaptic plasticityde_DE
dc.subjectpattern recognitionde_DE
dc.subject.ddc570: Biowissenschaften, Biologiede_DE
dc.titleIntegrated circuit with memristor emulator array and neuron circuits for biologically inspired neuromorphic pattern recognitionde_DE
dc.typeArticlede_DE
dc.identifier.urnurn:nbn:de:gbv:830-882.026562-
dc.identifier.doi10.15480/882.2018-
dc.type.diniarticle-
dc.subject.ddccode570-
dcterms.DCMITypeText-
tuhh.identifier.urnurn:nbn:de:gbv:830-882.026562-
tuhh.oai.showtruede_DE
tuhh.abstract.englishThis paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88ns to 4.99μs (200kOhm) to 204.8MOhm)) and other four having conductance ranging from 195ns to 190μs (5.2kOhm) to 5.12MOhm)). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350nm process.de_DE
tuhh.publisher.doi10.1142/S0218126617501833-
tuhh.publication.instituteIntegrierte Schaltungen E-9de_DE
tuhh.identifier.doi10.15480/882.2018-
tuhh.type.opus(wissenschaftlicher) Artikel-
tuhh.institute.germanIntegrierte Schaltungen E-9de
tuhh.institute.englishIntegrierte Schaltungen E-9de_DE
tuhh.gvk.hasppnfalse-
openaire.rightsinfo:eu-repo/semantics/openAccessde_DE
dc.type.driverarticle-
dc.rights.ccversion4.0de_DE
dc.type.casraiJournal Article-
tuhh.container.issue11de_DE
tuhh.container.volume26de_DE
tuhh.container.startpage1750183de_DE
dc.relation.projectFOR 2093: Memristive Bauelemente für neuronale Systeme, Teilprojekt C2 "Neuronale Schaltungen"de_DE
dc.rights.nationallicensefalsede_DE
dc.identifier.scopus2-s2.0-85020195902-
local.status.inpressfalsede_DE
local.funding.infoDeutsche Forschungsgemeinschaft (DFG)de_DE
datacite.resourceTypeJournal Article-
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item.mappedtypeArticle-
item.openairetypeArticle-
item.languageiso639-1en-
item.grantfulltextopen-
item.cerifentitytypePublications-
item.creatorOrcidRanjan, Rajeev-
item.creatorOrcidMendoza Ponce, Pablo-
item.creatorOrcidHellweg, Wolf Lukas-
item.creatorOrcidKyrmanidis, Alexandros-
item.creatorOrcidAbu Saleh, Lait-
item.creatorOrcidSchroeder, Dietmar-
item.creatorOrcidKrautschneider, Wolfgang H.-
item.creatorGNDRanjan, Rajeev-
item.creatorGNDMendoza Ponce, Pablo-
item.creatorGNDHellweg, Wolf Lukas-
item.creatorGNDKyrmanidis, Alexandros-
item.creatorGNDAbu Saleh, Lait-
item.creatorGNDSchroeder, Dietmar-
item.creatorGNDKrautschneider, Wolfgang H.-
item.fulltextWith Fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_6501-
crisitem.project.funderDeutsche Forschungsgemeinschaft (DFG)-
crisitem.project.funderid501100001659-
crisitem.project.funderrorid018mejw64-
crisitem.project.grantnoKR 3281/8-3-
crisitem.author.deptIntegrierte Schaltungen E-9-
crisitem.author.deptIntegrierte Schaltungen E-9-
crisitem.author.deptIntegrierte Schaltungen E-9-
crisitem.author.deptIntegrierte Schaltungen E-9-
crisitem.author.deptIntegrierte Schaltungen E-9-
crisitem.author.deptIntegrierte Schaltungen E-9-
crisitem.author.deptIntegrierte Schaltungen E-9-
crisitem.author.orcid0000-0003-1048-577X-
crisitem.author.orcid0000-0001-5891-3628-
crisitem.author.orcid0000-0001-8629-4545-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik (E)-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik (E)-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik (E)-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik (E)-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik (E)-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik (E)-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik (E)-
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