Exploiting Locality for the Performance Analysis of Shared Memory Systems in MPSoCs

Publikationstyp
Conference Paper
Date Issued
2018-12
Sprache
English
Author(s)
Saidi, Selma  
Syring, Alexander  
Institut
Eingebettete Systeme E-13  
TORE-URI
http://hdl.handle.net/11420/2160
Start Page
350
End Page
360
Citation
Real-Time Systems Symposium: 350-360 (2018)
Contribution to Conference
39th IEEE Real-Time Systems Symposium, RTSS 2018  
Publisher DOI
10.1109/RTSS.2018.00050
Scopus ID
2-s2.0-85061537965
Publisher
IEEE
The integration trend and increased required computing power is driving the advent of common embedded consumer devices like MPSoCs platforms in the safety critical domain. MPSoCs often feature a shared tightly-coupled memory system where a careful management of data storage and transfers is a key enabler for performance. However, providing real-time guarantees for these platforms is extremely challenging as they rely on exploiting data locality to improve average latencies in shared-memory architectures. This effect is often disregarded by existing real-time analysis approaches which furthermore often focus solely on a single component of the memory system. In this paper, we propose a framework for the timing analysis of shared memory systems composed of on-chip scratchpad memories, off-chip DRAMs and DMA engines. The analysis captures the effect on the performance of the system of the locality of accesses, their interleaving and granularity.
DDC Class
600: Technology