|Publisher DOI:||10.1109/RTSS.2018.00050||Title:||Exploiting Locality for the Performance Analysis of Shared Memory Systems in MPSoCs||Language:||English||Authors:||Saidi, Selma
|Issue Date:||4-Jan-2019||Source:||Proceedings - Real-Time Systems Symposium (2018-December): 350-360 (2019-01-04)||Journal or Series Name:||Proceedings - Real-Time Systems Symposium||Abstract (english):||The integration trend and increased required computing power is driving the advent of common embedded consumer devices like MPSoCs platforms in the safety critical domain. MPSoCs often feature a shared tightly-coupled memory system where a careful management of data storage and transfers is a key enabler for performance. However, providing real-time guarantees for these platforms is extremely challenging as they rely on exploiting data locality to improve average latencies in shared-memory architectures. This effect is often disregarded by existing real-time analysis approaches which furthermore often focus solely on a single component of the memory system. In this paper, we propose a framework for the timing analysis of shared memory systems composed of on-chip scratchpad memories, off-chip DRAMs and DMA engines. The analysis captures the effect on the performance of the system of the locality of accesses, their interleaving and granularity. © 2018 IEEE.||URI:||http://hdl.handle.net/11420/2160||ISBN:||978-153867907-4||ISSN:||1052-8725||Institute:||Eingebettete Systeme E-13||Type:||InProceedings (Aufsatz / Paper einer Konferenz etc.)|
|Appears in Collections:||Publications without fulltext|
Show full item record
checked on Sep 28, 2020
Add Files to Item
Note about this record
Items in TORE are protected by copyright, with all rights reserved, unless otherwise indicated.