Publisher DOI: 10.1109/DDECS.2018.00028
Title: Augmenting all solution SAT solving for circuits with structural information
Language: English
Authors: Tibebu, Abraham Temesgen 
Fey, Görschwin 
Issue Date: 11-Jul-2018
Source: Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 : 117-122 (2018-07-11)
Journal or Series Name: Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 
Abstract (english): All solutions SAT (All-SAT) is important in applications where we require enumerating all satisfying assignments of a propositional formula, e.g., when reasoning over many or all possible test patterns in Automatic Test Pattern Generation (ATPG). We applied structural analysis starting from primary inputs or primary outputs to generalize a current total assignment to a partial assignment. This speeds up the determination of all satisfying assignments. The experiments were conducted using a large number of random instances and different available All-SAT solvers. We show that structural analysis techniques can significantly speed up enumeration of all satisfying assignments of combinational circuits and yield the the second largest number of total satisfying assignments from all compared All-SAT solvers.
URI: http://hdl.handle.net/11420/2629
ISBN: 978-153865754-6
Institute: Eingebettete Systeme E-13 
Type: InProceedings (Aufsatz / Paper einer Konferenz etc.)
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