Symbolic circuit analysis under an arc based timing model

Publikationstyp
Conference Paper
Date Issued
2019-05
Author(s)
Fey, Görschwin  orcid-logo
Garcia-Ortiz, Alberto  
Institut
Eingebettete Systeme E-13  
TORE-URI
http://hdl.handle.net/11420/3266
Article Number
8791525
Citation
European Test Workshop: 8791525 (2019-05)
Contribution to Conference
IEEE European Test Symposium, ETS 2019  
Publisher DOI
10.1109/ETS.2019.8791525
Scopus ID
2-s2.0-85071167748
Tools for Automatic Test Pattern Generation (ATPG) typically abstract timing. When a more detailed timing model is needed, either simulation or statistic timing analysis is usually applied. Our symbolic engine based on Satisfiability Modulo Theories can reason over a model using pin-to-pin timing arcs as available after synthesis or after place and route. We study the differences of a simple fixed gate delay versus the arc-based timing model.