Publisher DOI: 10.1109/ETS.2019.8791525
Title: Symbolic circuit analysis under an arc based timing model
Authors: Fey, Görschwin  
Garcia-Ortiz, Alberto 
Issue Date: May-2019
Source: Proceedings of the European Test Workshop (2019-May): 8791525 (2019-05)
Journal or Series Name: Proceedings of the European Test Workshop 
Abstract (english): Tools for Automatic Test Pattern Generation (ATPG) typically abstract timing. When a more detailed timing model is needed, either simulation or statistic timing analysis is usually applied. Our symbolic engine based on Satisfiability Modulo Theories can reason over a model using pin-to-pin timing arcs as available after synthesis or after place and route. We study the differences of a simple fixed gate delay versus the arc-based timing model.
ISBN: 978-172811173-5
ISSN: 15301877
Institute: Eingebettete Systeme E-13 
Type: InProceedings (Aufsatz / Paper einer Konferenz etc.)
Appears in Collections:Publications without fulltext

Show full item record

Page view(s)

Last Week
Last month
checked on Sep 27, 2020

Google ScholarTM


Add Files to Item

Note about this record


Items in TORE are protected by copyright, with all rights reserved, unless otherwise indicated.