Cache-aware instruction SPM allocation for hard real-time systems

Publikationstyp
Conference Paper
Date Issued
2016-05-23
Sprache
English
Author(s)
Luppold, Arno  orcid-logo
Kittsteiner, Christina  
Falk, Heiko  orcid-logo
Institut
Eingebettete Systeme E-13  
TORE-URI
http://hdl.handle.net/11420/6251
Start Page
77
End Page
85
Citation
International Workshop on Software and Compilers for Embedded Systems, SCOPES: 77-85 (2016-05-23)
Contribution to Conference
19th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2016  
Publisher DOI
10.1145/2906363.2906369
Scopus ID
2-s2.0-84974604514
To improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.
Subjects
Compiler
Integer-linear programming
Optimization
Real-time
WCET