DC FieldValueLanguage
dc.contributor.authorLuppold, Arno-
dc.contributor.authorKittsteiner, Christina-
dc.contributor.authorFalk, Heiko-
dc.date.accessioned2020-06-05T12:40:28Z-
dc.date.available2020-06-05T12:40:28Z-
dc.date.issued2016-05-23-
dc.identifier.citationInternational Workshop on Software and Compilers for Embedded Systems, SCOPES: 77-85 (2016-05-23)de_DE
dc.identifier.isbn978-145034320-6de_DE
dc.identifier.urihttp://hdl.handle.net/11420/6251-
dc.description.abstractTo improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.en
dc.language.isoende_DE
dc.subjectCompilerde_DE
dc.subjectInteger-linear programmingde_DE
dc.subjectOptimizationde_DE
dc.subjectReal-timede_DE
dc.subjectWCETde_DE
dc.titleCache-aware instruction SPM allocation for hard real-time systemsde_DE
dc.typeinProceedingsde_DE
dc.type.dinicontributionToPeriodical-
dcterms.DCMITypeText-
tuhh.abstract.englishTo improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.de_DE
tuhh.publisher.doi10.1145/2906363.2906369-
tuhh.publication.instituteEingebettete Systeme E-13de_DE
tuhh.type.opusInProceedings (Aufsatz / Paper einer Konferenz etc.)-
dc.type.drivercontributionToPeriodical-
dc.type.casraiConference Paper-
tuhh.container.startpage77de_DE
tuhh.container.endpage85de_DE
dc.relation.conference19th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2016de_DE
item.creatorGNDLuppold, Arno-
item.creatorGNDKittsteiner, Christina-
item.creatorGNDFalk, Heiko-
item.openairecristypehttp://purl.org/coar/resource_type/c_5794-
item.grantfulltextnone-
item.languageiso639-1en-
item.openairetypeinProceedings-
item.cerifentitytypePublications-
item.creatorOrcidLuppold, Arno-
item.creatorOrcidKittsteiner, Christina-
item.creatorOrcidFalk, Heiko-
item.fulltextNo Fulltext-
crisitem.author.deptEingebettete Systeme E-13-
crisitem.author.deptEingebettete Systeme E-13-
crisitem.author.orcid0000-0001-8714-0273-
crisitem.author.orcid0000-0003-1196-0122-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik-
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