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Revisiting Explicit Enumeration for Exact Synthesis
Publikationstyp
Conference Paper
Date Issued
2020-08
Sprache
English
Author(s)
Institut
TORE-URI
Start Page
29
End Page
34
Article Number
9217643
Citation
Euromicro Conference on Digital System Design (DSD 2020)
Contribution to Conference
Publisher DOI
Scopus ID
The problem of generating a minimal implementation of a given Boolean function is called exact synthesis. The parameter to be minimized is often the total number of gates used for the implementation. The exact synthesis engine is considered an essential tool for most state-of-The-Art logic optimization flows. In this paper, we present an algorithm that, using enumeration over non-isomorphic graph structures, generates minimal circuits implementing specified Boolean functions using a set of predefined gate types. In our experiments, we show that our prototype implementation of this technique can be compared to state-of-The-Art tools for small functions. Moreover, we show that this technique can be parallelized effectively.
Subjects
enumeration
exact synthesis
logic synthesis
minimal circuits
DDC Class
600: Technology