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Item type:Publication, Access status: without files , A one-dimensional analog VLSI implementation for nonlinear real-time signal preprocessing(Academic Press, 2001); ; ; ; Reconstruction of given noisy data is an ill-posed problem and a computationally intensive task. Nonlinear regularization techniques are used to find a unique solution under certain constraints. In our contribution we present a parallel mixed-signal architecture which solves this nonlinear problem with in microseconds. By connecting all parallel cells in a circular manner it is possible to process noisy data vectors of infinite length. This is achieved by virtually shifting the nonlinear adaptive filter kernel over the noisy data vector. Additionally, we focus on the interaction between theory, discretization, numerical simulations, macro-modeling, and analog VLSI implementation for a theoretically well understood class of computer vision in an exemplary and paradigmatic way. A one-dimensional (ID) experimental chip has been fabricated using 0.8 μm CMOS technology. On-chip measurements are shown to agree with results from numerical simulations. Results from applying the ID chip to nonlinear smoothing of two-dimensional image data will also be given correspondence. © 2001 Academic Press.Publicationtype: Journal Article92 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Real-time adaptive smoothing with a 1-D non-linear relaxation network in analogue VLSI technology(Springer, 1998-09); ; ; ; Publicationtype: Conference Paper25 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Dynamic circular cellular networks for adaptive smoothing of multi-dimensional signalsIn [10] a theoretical framework for locally-adaptive smoothing of multi-dimensional data was presented. Based on this framework we introduce a hardware efficient architecture suitable for mixed-mode VLSI implementation. Substantial shortcomings of analogue implementations are overcome by connecting all cells in a circular structure: i) influence of process parameter deviation ii) limited number of cells iii) input/output bottleneck. The connections between the analogue cells and the cells themselves are dynamically reconfigured. This results in a non-linear adaptive filter kernel which is shifted virtually over the signal vector of infinite length. A 1-d prototype with 32 cells has been fabricated using 0.8 μm CMOS-technology. The chip is fully functional with an overall error less than 1%; experimental results are presented in this paper.Publicationtype: Conference Paper29