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Item type:Publication, Access status: without files , ANN Hyperparameter Optimization by Genetic Algorithms for Via Interconnect ClassificationIn an imbalanced classification problem the distribution of data across the known classes is biased or skewed. It poses a challenge for predictive modeling as most of the machine learning algorithms used for classification were designed around the assumption of an equal number of examples for each class. In this paper, we propose an approach to solve via interconnect classification problems by artificial neural networks, where the optimum hyperparameters of the networks are searched through a genetic algorithm. We solve the binary imbalanced classification problem for vias in time domain and frequency domain, including single and multilabel cases. Imbalanced learning techniques, like random oversampling and weighted binary crossentropy, are studied in combination with the genetic algorithm. We found standardization, F-measure, and imbalanced learning techniques are suitable to deal with minority label classification for this kind of signal integrity problems. The overall accuracy of our method is above 97%.Publicationtype: Conference Paper66 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , SI/PI-database of PCB-based interconnects for machine learning applications(IEEE, 2021-02-24); ; ; ; A database is presented that allows the investigation of machine learning (ML) tools and techniques in the signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) domains. The database contains different types of printed circuit board (PCB)-based interconnects and corresponding frequency domain data from a physics-based (PB) tool and represent multiple electromagnetic (EM) aspects to SI and PI optimization. The interconnects have been used in the past by the authors to investigate ML techniques in SI and PI. However, many more tools and techniques can be developed and applied to these structures. The setup of the database, its data sets, and examples on how to apply ML techniques to the data will be discussed in detail. Overall 78961 variations of interconnects are presented. By making this database available we invite other researchers to apply and customize their ML techniques using our results. This provides the possibility to accelerate ML research in EMC engineering without the need to generate expensive data.Publicationtype: Journal ArticleScopus© Citations 20 168 315 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Mode Conversion Due to Residual Via Stubs in Differential SignalingMode conversion is an important source of degradation in differential links, which can be induced by a trace length mismatch or asymmetric ground via configurations. This paper explores another source of mode conversion caused by asymmetric residual via stubs. These remnant via stubs can be present because of multiple reasons, such as residual stubs due to process tolerances or errors during back-drilling. Different via configurations have been analyzed through full-wave simulations. Results show a large impact on mode conversion with an increment of around -35 and -15 dB when the residual stub difference changes from 2 to 14 mil at the fundamental frequency of 17.5 GHz. Furthermore, an estimation approach of mode conversion as a function of via stub asymmetry is proposed.Publicationtype: Conference Paper643 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Via Transition Optimization Using a Domain Decomposition ApproachA method to minimize the return loss for via interconnects on printed circuit boards (PCB), based on the domain decomposition of traces, via barrels, and trace-to-via transitions is presented. This decomposition allows to optimize different via lengths, by separating the via barrel as an independent domain. The method is demonstrated by full-wave simulations. It starts by optimizing the via impedance, matching the traces by an appropriate size of the via environment followed by a subsequent compensation of trace-to-via transition discontinuities. Equivalent circuits of each domain are used to corroborate the performance improvement. Three pad geometries are proposed to compensate the discontinuities of a trace-to-via transition. For a long via on a PCB with eleven metal layers, using four ground vias, it was possible to achieve a wide-band low-reflection response below -30 dB from DC up to 32 GHz for microstrip traces and -37 dB from DC up to 20 GHz for stripline traces.Publicationtype: Conference Paper138