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Item type:Publication, Access status: without files , CubeSat LAB - From Hamburg to SpaceThe space sector is expanding rapidly and requires a new generation of students to recognise space as a distinct engineering discipline, rather than perceiving it as ‘rocket science’. Hamburg is known for its aviation and maritime industries, which is reflected in the education at the Hamburg University of Technology. Enabling interdisciplinary space education and especially fostering self-learning in electronics and computer science topics at the TU Hamburg is the goal of the EduSat Project of the Smart Sensors Group. This is achieved by a combination of lectures, Project-based learning and the CubeSat LAB, the latter providing students with the opportunity to build their own payload, work on a provided cubesat and expose students to the space sector. The CubeSat LAB is unique in its focus on the electronics of a cubesat, caused by a lack of pre-existing space engineering curricula at our university. This lack of theoretical space engineering knowledge is one of the challenges the LAB, and its students, faces. Further this means students have to transfer and apply their theoretical knowledge to the space domain. The goal of the LAB is to offer physical and intellectual space for students from various backgrounds and study levels to work together interdisciplinarily and get in contact with the space sector and its engineering challenges, beyond their curriculum. Furthermore, working in different subteams, communicating with each other, and solving challenges in a bigger team prepares the students for their future career. While the CubeSat LAB is part of the Smart Sensors Group, it is governed by students, whereas tutors are supervising the team and providing the interface to the group. The current student mission aims to autonomously capture the northern lights, with the help of a variety of sensors. The team is close to the end of the concept phase, working to expand participation and has founded an association to support their efforts. Further the students are participating in the REXUS program, with a LiFi-based experiment. This paper presents the structure, challenges, and first outcomes of the CubeSat LAB, presenting its role in space education at the TU Hamburg and promoting interdisciplinary engagement with the space sector.Publicationtype: Conference Paper8 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , Short paper: simulation-based performance characterization of common NOR flash file systems(Association for Computing Machinery (ACM), 2026-05); ; NOR flash memory is widely used as storage in embedded systems as it offers dense non-volatile memory up to the gigabit range while being more reliable than NAND flash. To avoid the cost of a standalone flash controller in such small systems, specialized flash file systems are used to handle the limited write endurance and asymmetric program/erase characteristics. While many NOR file systems exist and are extensively deployed, there is a lack of systematic comparisons of their performance. In this paper, we present vflashsim, a simulator for capturing interactions between file systems and flash memory and for running representative benchmarks. Unlike evaluations on physical hardware, our simulation-based approach avoids prohibitively long erase latencies and cell wear. We implement a NOR flash model and, using vflashsim, evaluate four representative file systems, SPIFFS, LittleFS, YAFFS2, and NF2FS, in terms of write amplification, garbage-collection behavior, and RAM utilization. Our analysis shows how design choices and implementation bugs, such as excessive device scanning, unconditional sector erases, and a lack of garbage collection in allocation paths, cause substantial performance issues. Additionally, we identify how to provoke failure conditions in different file systems, which can result in unrecoverable crashes. Among the evaluated file systems, YAFFS demonstrates the best overall performance and reliability at the cost of high RAM usage, whereas a modified LittleFS remains the best option for more memory-constrained systems. Since performance trade-offs vary by workload and hardware constraints, no single file system is universally optimal. With vflashsim, we provide a tool that enables developers and users of flash file systems to analyze their behavior under diverse configurations and workloads.Publicationtype: Conference Paper20 13 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Virtual-memory assisted buffer management(Association for Computing Machinery (ACM), 2023); ; ; ; Most database management systems cache pages from storage in a main memory buffer pool. To do this, they either rely on a hash table that translates page identifiers into pointers, or on pointer swizzling which avoids this translation. In this work, we propose vmcache, a buffer manager design that instead uses hardware-supported virtual memory to translate page identifiers to virtual memory addresses. In contrast to existing mmap-based approaches, the DBMS retains control over page faulting and eviction. Our design is portable across modern operating systems, supports arbitrary graph data, enables variable-sized pages, and is easy to implement. One downside of relying on virtual memory is that with fast storage devices the existing operating system primitives for manipulating the page table can become a performance bottleneck. As a second contribution, we therefore propose exmap, which implements scalable page table manipulation on Linux. Together, vmcache and exmap provide flexible, efficient, and scalable buffer management on multi-core CPUs and fast storage devices.Publicationtype: Conference Paper115 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , Evaluation and refinement of an explicit virtual-memory primitiveThe general-purpose virtual-memory subsystem of Linux does not scale to the multimillion IOP/s SSDs of today. Further, its implicit write-back and back-fill semantic hinders data-intensive applications, like databases, more than it actually helps. In contrast, explicit virtual-memory abstractions, as introduced by ExMap, provide an Exokernel-like interface to manipulate theVMsurface. Thereby, the user application remains in full control over the VM surface and can benefit from low operation latencies. In this paper, we investigate the performance of the existing ExMap abstraction and propose enhancements for its system-call interface, its process-local memory pool management, and the user-space page-state tracking. With memory-mapped I/O vectors, the global bundle list, and exported page tables, we improve the end-toend throughput of in-memory random B+tree lookups by up to 5.7 percent, while the out-of-memory case improves by up to 4.9 percent.Publicationtype: Journal Article40 52 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , SailFAIL: Model-Derived Simulation-Assisted ISA-Level Fault-Injection PlatformsFor systematic fault injection (FI), we deterministically re-execute a program, introduce faults, and observe the program outcome to assess its resilience in the presence of transient hardware faults. For this, simulation-assisted ISA-level FI provides a good trade-off between result quality and the required time to execute the FI campaign. However, for each architecture, this requires a specialized ISA simulator with tracing, injection, and error observation capabilities; a dependency that not only increases the bar for the exploration of ISA-level hardening mechanisms, but which can also deviate from the behavior of the actual hardware, especially when an error propagates through the system and triggers semantic edge cases. With SailFAIL, we propose a model-driven approach to derive FI platforms from Sail models, which formally describe the ISA semantics. Based on two existing (RISC-V, CHERI RISC-V) and one newly introduced (AVR) Sail models, we use the Sail toolchain to derive emulators that we combine with the FAIL* framework into multiple new FI platforms. Furthermore, we extend Sail to automatically introduce bit-wise dynamic register tracing into the emulator, which enables us to harvest bit-wise access information that we use to improve the well-known def-use pruning technique. Thereby, we further reduce the number of necessary injections by up to 19%.Publicationtype: Conference Paper41