DC FieldValueLanguage
dc.contributor.authorMarotzke, Adrian-
dc.date.accessioned2021-10-13T17:56:34Z-
dc.date.available2021-10-13T17:56:34Z-
dc.date.issued2020-11-
dc.identifier.citationInternational Conference on Smart Card Research and Advanced Applications (CARDIS 2020)de_DE
dc.identifier.isbn9783030684860de_DE
dc.identifier.issn0302-9743de_DE
dc.identifier.urihttp://hdl.handle.net/11420/10515-
dc.description.abstractThis paper presents a constant time hardware implementation of the NIST round 2 post-quantum cryptographic algorithm Streamlined NTRU Prime. We implement the entire KEM algorithm, including all steps for key generation, encapsulation and decapsulation, and all en- and decoding. We focus on optimizing the resources used, as well as applying optimization and parallelism available due to the hardware design. We show the core en- and decapsulation requires only a fraction of the total FPGA fabric resource cost, which is dominated by that of the hash function, and the en- and decoding algorithm. For the NIST Security Level 3, our implementation uses a total of 1841 slices on a Xilinx Zynq Ultrascale+ FPGA, together with 14 BRAMs and 19 DSPs. The maximum achieved frequency is 271 MHz, at which the key generation, encapsulation and decapsulation take 4808 μ s, 524 μ s and 958 μ s respectively. To our knowledge, this work is the first full hardware implementation where the entire algorithm is implemented.en
dc.language.isoende_DE
dc.relation.ispartofLecture notes in computer sciencede_DE
dc.subjectFPGAde_DE
dc.subjectHardwarede_DE
dc.subjectKey encapsulation mechanismde_DE
dc.subjectLattice-based cryptographyde_DE
dc.subjectNTRU Primede_DE
dc.subjectPost-quantum cryptographyde_DE
dc.subjectVHDLde_DE
dc.titleA Constant Time Full Hardware Implementation of Streamlined NTRU Primede_DE
dc.typeinProceedingsde_DE
dc.type.dinicontributionToPeriodical-
dcterms.DCMITypeText-
tuhh.abstract.englishThis paper presents a constant time hardware implementation of the NIST round 2 post-quantum cryptographic algorithm Streamlined NTRU Prime. We implement the entire KEM algorithm, including all steps for key generation, encapsulation and decapsulation, and all en- and decoding. We focus on optimizing the resources used, as well as applying optimization and parallelism available due to the hardware design. We show the core en- and decapsulation requires only a fraction of the total FPGA fabric resource cost, which is dominated by that of the hash function, and the en- and decoding algorithm. For the NIST Security Level 3, our implementation uses a total of 1841 slices on a Xilinx Zynq Ultrascale+ FPGA, together with 14 BRAMs and 19 DSPs. The maximum achieved frequency is 271 MHz, at which the key generation, encapsulation and decapsulation take 4808 μ s, 524 μ s and 958 μ s respectively. To our knowledge, this work is the first full hardware implementation where the entire algorithm is implemented.de_DE
tuhh.publisher.doi10.1007/978-3-030-68487-7_1-
tuhh.type.opusInProceedings (Aufsatz / Paper einer Konferenz etc.)-
dc.type.drivercontributionToPeriodical-
dc.type.casraiConference Paper-
tuhh.container.volume12609 LNCSde_DE
tuhh.container.startpage3de_DE
tuhh.container.endpage17de_DE
dc.relation.conference19th International Conference on Smart Card Research and Advanced Applications, CARDIS 2020de_DE
dc.identifier.scopus2-s2.0-85101851850de_DE
item.openairecristypehttp://purl.org/coar/resource_type/c_5794-
item.creatorOrcidMarotzke, Adrian-
item.cerifentitytypePublications-
item.mappedtypeinProceedings-
item.openairetypeinProceedings-
item.fulltextNo Fulltext-
item.grantfulltextnone-
item.creatorGNDMarotzke, Adrian-
item.languageiso639-1en-
Appears in Collections:Publications without fulltext
Show simple item record

Page view(s)

25
Last Week
5
Last month
5
checked on Dec 8, 2021

Google ScholarTM

Check

Add Files to Item

Note about this record

Cite this record

Export

Items in TORE are protected by copyright, with all rights reserved, unless otherwise indicated.