Please use this identifier to cite or link to this item: https://doi.org/10.15480/882.1575
This item is licensed with a CreativeCommons licence by/3.0
Publisher DOI: 10.1155/2010/357839
Title: A decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier on a Virtex-5 FPGA
Language: English
Authors: Baesler, Malte 
Voigt, Sven-Ole 
Teufel, Thomas 
Keywords: decimal floating point operation
Issue Date: 23-Dec-2010
Publisher: Hindawi Publishing Corporation
Source: International Journal of Reconfigurable Computing, vol. 2010, Article ID 357839, 13 pages
Journal or Series Name: International Journal of Reconfigurable Computing 
Abstract (english): Decimal Floating Point operations are important for applications that cannot tolerate errors from conversionsbetween binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, wepresent a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is basedon BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipelinestages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unitfor IEEE 754-2008 decimal64 data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unitand migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accuratescalar product unit's latency even by a factor of five.
URI: http://tubdok.tub.tuhh.de/handle/11420/1578
DOI: 10.15480/882.1575
ISSN: 1687-7209
Institute: Zuverlässiges Rechnen E-19 
Type: (wissenschaftlicher) Artikel
Appears in Collections:Publications (tub.dok)

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