The impact of time delays for power hardware-in-the-loop investigations

Enthalten in
Energies 
Volume
14
Issue
11
Article Number
3154
Citation
Energies 14 (11): 3154 (2021-06-01)
Publisher DOI
10.3390/en14113154
Scopus ID
2-s2.0-85107829957
Publisher
Multidisciplinary Digital Publishing Institute
Power hardware-in-the-loop (PHiL) simulations provide a powerful environment in the critical process of testing new components and controllers. In this work, we aim to explain the impact of time delays in a PHiL setup and recommend how to consider them in different investigations. The general concept of PHiL, with its necessary components, is explained and the benefits compared to pure simulation and implemented field tests are presented. An example for a flexible PHiL environment is shown in form of the Power Hardware-in-the-Loop Simulation Laboratory (PHiLsLab) at TU Hamburg. In the PHiLsLab, different hardware components are used as the simulator to provide a grid interface via an amplifier system, a real-time simulator by OPAL-RT, a programmable logic controller by Bachmann, and an M-DUINO microcontroller. Benefits and limitations of the different simulators are shown using case examples of conducted investigations. Essentially, all platforms prove to be appropriate and sufficiently powerful simulators, if the time constants and complexity of the investigated case fit the simulator performance. The communication interfaces used between simulator and amplifier system differ in communication speed and delay; therefore, they have to be considered to determine the level of dynamic interactions between the simulated rest of system and the hardware under test.
Schlagworte
power hardware-in-the-loop (PHiL)
communication protocols
time delays
modeling and simulation
hardware under test (HUT)
rest of system (ROS)
DDC Class
600: Technik
620: Ingenieurwissenschaften