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    Item type:Publication, Access status: without files ,
    Ageing analysis of embedded SRAM on a large-scale testbed using machine learning
    (IEEE, 2023)
    Lanzieri, Leandro
    ;
    Kietzmann, Peter
    ;
    Fey, Görschwin
    ;
    Schmidt, Thomas C.
    ;
    Schlarb, Holger
    Ageing detection and failure prediction are essential in many Internet of Things (IoT) deployments, which operate huge quantities of embedded devices unattended in the field for years. In this paper, we present a large-scale empirical analysis of natural SRAM wear-out using 154 boards from a generalpurpose testbed. Starting from SRAM initialization bias, which each node can easily collect at startup, we apply various metrics for feature extraction and experiment with common machine learning methods to predict the age of operation for this node. Our findings indicate that even though ageing impacts are subtle, our indicators can well estimate usage times with an R2 score of 0.77 and a mean error of 24% using regressors, and with an Fl score above 0.6 for classifiers applying a six-months resolution.
    Publicationtype: Conference Paper
      19
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    Latency-optimized hardware acceleration of multilayer perceptron inference
    (IEEE, 2023)
    Zoubi, Ahmad al-
    ;
    Schaible, Benedikt
    ;
    Martino, Gianluca
    ;
    Fey, Görschwin
    Decreasing the inference latency of neural networks is crucial in situations where real-time responses are necessary. We propose a new neuron architecture for parallel computations, targeting the MLP implementation on an FPGA. The parallelism in the proposed architecture is exposed through the segmentation of non-linear activation functions into a set of linear segments, delivering highly accurate estimations of the original function. The implementation combines various other optimization techniques, such as fixed-point arithmetics, pipelining, array partitioning, and loop unrolling. For the validation of the proposed architecture using the Xilinx Vitis HLS toolchain, four MLPs with a mix of non-linear activation functions have been implemented and evaluated in comparison to accelerated models produced by the open-source tool hls4ml, a Python package for latency-optimized machine learning inference in FPGAs. Experimental results clearly show that our proposed architecture outperformed the corresponding hls4ml model with up to three times speedups.
    Publicationtype: Conference Paper
      18