Now showing1 - 10 of 19
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    Item type:Publication,
    Work in progress : optimizing schedulability using cache-bypassing
    (IEEE, 2025-05) ;
    We present an optimization technique to improve system schedulability using selective cache bypassing. By allocating parts of the application to uncached memory sections during compilation, context-switching costs and intra-task cache interference are reduced, leading to improved schedulability. We compare the performance of simulated annealing and the strength pareto evolutionary algorithm (SPEA) for the optimization problem. Our evaluation demonstrates an increase in schedulability by up to 20 percentage points using SPEA.
    Publicationtype: Conference Paper
      8
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    Report on the 2023 Embedded Systems Week (ESWEEK)
    (IEEE, 2024-04-01) ; ;
    Embedded Systems Week (ESWEEK) is the premier worldwide event covering all aspects of embedded systems, encompassing software, hardware, and codesign aspects. Since its creation in 2005, it has gathered three leading conferences (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES; International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS; and International Conference on Embedded Software, EMSOFT) along with several colocated events, to offer, to the attendees, a wide range of choices unveiling state-of-the-art embedded systems design and hardware/software architectures.
    Publicationtype: Report
      9
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    Shared cache analysis under preemptive scheduling
    (IEEE, 2024) ;
    When sharing a cache between multiple cores, the inter-core interference has to be considered in the worst-case execution time (WCET) analysis. Current interference models are overly pessimistic or not applicable to preemptively scheduled systems. We propose a novel technique to model interference in a preemptive system to classify accesses as cache hits or potential misses. We account for inter-core interference by considering the potential execution scenarios on the interfering core and find the worst-case interference pattern. The resulting access classifications are then used to compute the cache-related preemption delay. Our evaluation shows that the proposed analysis significantly increases the cache hit classifications, reduces WCET on average by up to 11.7%, and reduces worst-case response times on average by up to 15.4% compared to the existing classification technique.
    Publicationtype: Conference Paper
      31
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    WCET Analysis of shared caches in multi-core architectures using event-arrival curves
    (IEEE, 2023) ;
    We propose a novel analysis approach for shared LRU caches to classify accesses as definitive cache hits or potential misses. In this approach inter-core cache interference is modelled as an event stream. Thus, by analyzing the timing between subsequent accesses to a particular cache block, it is possible to bound the inter-core interference. This perspective allows us to classify accesses as cache hits or potential misses using a data-flow analysis. We compare the performance of the presented approach to a partitioning of the shared cache.
    Publicationtype: Conference Paper
      14
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    The TeamPlay Project: Analysing and optimising time, energy, and security for Cyber-Physical Systems
    (IEEE, 2023)
    Rouxel, Benjamin
    ;
    Brown, Christopher
    ;
    ; ;
    Non-functional properties, such as energy, time, and security (ETS) are becoming increasingly important in Cyber-Physical Systems (CPS) programming. This article describes TeamPlay, a research project funded under the EU Horizon 2020 programme between January 2018 and June 2021. TeamPlay aimed to provide the system designer with a toolchain for developing embedded applications where ETS properties are first-class citizens, allowing the developer to reflect directly on energy, time and security properties at the source code level. In this paper we give an overview of the TeamPlay methodology, introduce the challenges and solutions of our approach and summarise the results achieved. Overall, applying our TeamPlay methodology led to an improvement of up to 18% performance and 52% energy usage over traditional approaches.
    Publicationtype: Conference Paper
      16
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    Predicting Objectives on a Reduced Search Space of Multiobjective Function Inlining
    (2021-11) ;
    The Worst-Case Execution Time (WCET), energy consumption, and code size are among the most important criteria of hard real-time systems. To estimate the WCET and energy consumption at compile time, static analyzers are often used: they estimate the objectives by invoking time-consuming microarchitecture, data flow, and control flow analyses. The expensive analyses make it almost infeasible to use evolutionary algorithms for solving multiobjective problems with these two objectives at compile time, since any evolutionary algorithm extensively evaluates objectives to find solutions. We propose a method that speeds up an evolutionary algorithm supplying it with a reduced search space and prediction model fitted on the reduced search space, so the algorithm needs to explore a smaller search space and can use fast predictions instead of time-consuming estimations to evaluate the WCET and energy consumption. The proposed approach is general enough to be used for any compiler-based optimization. We demonstrate the advantages of it solving a multiobjective function inlining problem at compile time.
    Publicationtype: Conference Paper
      44
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    Predicting Worst-Case Execution Times During Multi-criterial Function Inlining
    (2021-10) ;
    In the domain of hard real-time systems, the Worst-Case Execution Time (WCET) is one of the most important design criteria. Safely and accurately estimating the WCET during a static WCET analysis is computationally demanding because of the involved data flow, control flow, and microarchitecture analyses. This becomes critical in the field of multi-criterial compiler optimizations that trade the WCET with other design objectives. Evolutionary algorithms are typically exploited to solve a multi-objective optimization problem, but they require an extensive evaluation of the objectives to explore the search space of the problem. This paper proposes a method that utilizes machine learning to build a surrogate model in order to quickly predict the WCET instead of costly estimating it using static WCET analysis. We build a prediction model that is independent of the source code and assembly code features, so a compiler can utilize it to perform any compiler-based optimization. We demonstrate the effectiveness of our model on multi-criterial function inlining, where we aim to explore trade-offs between the WCET, code size, and energy consumption at compile time.
    Publicationtype: Conference Paper
      49
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    Work-In-Progress: Fine-Grained On-Chip Energy Measurement of a Real-Time Multi-Core Processor
    Embedded systems are often constrained by their energy consumption. To create energy-efficient software or to validate worst-case energy behavior, sophisticated energy models can be used. Measuring the energy consumption of a processor on a fine-grained level for an energy model typically requires the design of custom measurement hardware. In this paper we present a simple measurement setup using the on-chip ADC of a TriCore AURIX TC277 multi-core processor, utilizing one core as a measurement core without the need of external or additional HW. We show that with this setup, a reasonable level of accuracy can be achieved. Furthermore, this also enables on-line power measurements
    Publicationtype: Conference Paper
      105
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    Multi-criteria function inlining for hard real-time systems
    (Association for Computing Machinery (ACM), 2020-06) ;
    Modern hard real-time systems shall satisfy some special requirements. Besides timing constraints, the additional design criteria such as code size and energy consumption are also not negligible. To optimize a system towards the mentioned specifications simultaneously is impossible, since the improvement in one of them may lead to the degradation of others. Many compiler-based optimizations techniques have been proposed to optimize an embedded application taking into account only one requirement. Nevertheless, some heuristics consider other requirements as constraints, but not many works have tried to solve a multi-objective problem in this context. We aim to extend a well-known compiler-based optimization, function inlining, to a multi-objective problem. We show that in case of such setup, the considered optimization leads to a set of trade-offs between timing constraints, code size, and energy consumption. Depending on the requirements, a system designer can utilize the output set to make a final decision about the system configuration without building an expensive hardware.
    Publicationtype: Conference Paper
      293
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    Compiler-based WCET prediction performing function specialization
    (2020-05-25) ;
    The Worst-Case Execution Time (WCET) is one of the most important criteria of hard real-time systems. Many optimizations have been proposed to improve WCET of an embedded application at compile time. Moreover, since modern embedded systems must also satisfy the additional design criteria like, e.g., code size or energy consumption, more often the compiler's optimizations go towards multi-objective optimization problems. Evolutionary algorithms are the most widely used method to solve a multi-objective problem. In order to find the set of the best trade-offs between the objectives, any evolutionary algorithm requires extensive evaluations of the objective functions. Thus, considering WCET as an objective in a multi-objective problem is infeasible in many cases, because the WCET analysis at compile time can be very time-consuming. For this reason, we propose a method based on a machine learning technique to predict the values of WCET at compile time. A well-known compiler-based optimization, function specialization, is considered as a base for the proposed prediction model. A regression method is analyzed in terms of making WCET predictions as precise as possible performing function specialization.
    Publicationtype: Conference Paper
      106