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Item type:Publication, Access status: without files , Work in progress : optimizing schedulability using cache-bypassingWe present an optimization technique to improve system schedulability using selective cache bypassing. By allocating parts of the application to uncached memory sections during compilation, context-switching costs and intra-task cache interference are reduced, leading to improved schedulability. We compare the performance of simulated annealing and the strength pareto evolutionary algorithm (SPEA) for the optimization problem. Our evaluation demonstrates an increase in schedulability by up to 20 percentage points using SPEA.Publicationtype: Conference Paper8 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Multi-criteria function inlining for hard real-time systemsModern hard real-time systems shall satisfy some special requirements. Besides timing constraints, the additional design criteria such as code size and energy consumption are also not negligible. To optimize a system towards the mentioned specifications simultaneously is impossible, since the improvement in one of them may lead to the degradation of others. Many compiler-based optimizations techniques have been proposed to optimize an embedded application taking into account only one requirement. Nevertheless, some heuristics consider other requirements as constraints, but not many works have tried to solve a multi-objective problem in this context. We aim to extend a well-known compiler-based optimization, function inlining, to a multi-objective problem. We show that in case of such setup, the considered optimization leads to a set of trade-offs between timing constraints, code size, and energy consumption. Depending on the requirements, a system designer can utilize the output set to make a final decision about the system configuration without building an expensive hardware.Publicationtype: Conference Paper293 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , Compilation for real-time systems : an overview of the WCET-aware C compiler WCC(2018-07); ; Traditionally, design of embedded hard real-time software and timing analysis are decoupled from each other, leading to complicated design flows involving human interaction. Furthermore, traditional compilers optimize for average-case performance so that no tool support exists supporting the designer to systematically reduce Worst-Case Execution Times in case that deadlines are missed. The WCET-Aware C Compiler WCC improves this situation by tightly schedulability analyses into the compilation and optimization flow. Furthermore, the compiler features dedicated real-time aware optimizations and exploits detailed architectural knowledge so that schedulable code meeting deadlines can be generated automatically, even for multitask or multicore systems.Publicationtype: Working Paper332 365 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , Bus-aware static instruction SPM allocation for multicore hard real-time systems(Schloss Dagstuhl - Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing, 2017-06-01); ; Over the past years, multicore systems emerged into the domain of hard real-time systems. These systems introduce common buses and shared memories which heavily influence the timing behavior. We show that existing WCET optimizations may lead to suboptimal results when applied to multicore setups. Additionally we provide both a genetic and a precise Integer Linear Programming (ILP)-based static instruction scratchpad memory allocation optimization which are capable of exploiting multicore properties, resulting in a WCET reduction of 26% in average compared with a bus-unaware optimization. Furthermore, we show that our ILP-based optimization's average runtime is distinctively lower in comparison to the genetic approach. Although limiting the number of tasks per core to one and partially exploiting private instruction SPMs, we cover the most crucial elements of a multicore setup: the interconnection and shared resources.Publicationtype: Conference PaperScopus© Citations 13 175 112 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Practical challenges of ILP-based SPM allocation optimizations(2016-05-23); ; Scratchpad Memory (SPM) allocation is a well-known technique for compiler-based code optimizations. Integer-Linear Programming has been proven to be a powerful technique to determine which parts of a program should be moved to the SPM. Although the idea is quite straight-forward in theory, the technique features several challenges when being applied to modern embedded systems. In this paper, we aim to bring out the main issues and possible solutions which arise when trying to apply those optimizations to existing hardware platforms.Publicationtype: Conference Paper71 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Cache-aware instruction SPM allocation for hard real-time systems(2016-05-23); ; To improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.Publicationtype: Conference Paper76