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Item type:Publication, Access status: without files , Integrating multi-/many-cores in avionics: Open issues and future conceptsPublicationtype: Conference Paper137 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Towards an Increased Detection Sensitivity of Time-Delay Attacks on Precision Time ProtocolPrecision time protocol (PTP) is one of the most widely used protocols for clock synchronization in packet-switched networks, on which, among others, the transaction synchronization of the stock markets relies. PTP was not standardized with security as a core requirement and is therefore vulnerable and attractive to manifold kinds of malicious attacks, such as time-delay attacks (TDAs). TDAs, in short, corrupt the exchange of timestamped messages and thus cause an incorrect synchronization process. The annex P of the IEEE 1588-2019 standard has defined a number of security mechanisms for clock synchronization, but, however, none of these can protect a PTP-based system completely against TDAs. In this work, we enhance existing approaches by introducing a so-called observation task and analytically deriving attack parameters of an ongoing TDA. Following the recommendation of the annex P of the IEEE 1588-2019 standard, these attack parameters can serve as an additional input for intrusion detection systems and allow for a more reliable and sensitive detection of TDAs. In a comprehensive evaluation, we experimentally investigate the impact different attack parameter combinations can have on a system.Publicationtype: Journal Article28 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Bridging the gap between resilient networks-on-chip and real-time systemsIEEE Conventional fault-tolerance approaches for Networks-on-Chip (NoCs) cannot be applied to high dependability systems due to their different goals and constraints. These systems impose strict integrity, resilience and real-time requirements. In order to meet these requirements, all possible effects of random hardware errors must be taken into account, silent data corruption must be prevented and the resulting system must be predictable in the presence of errors. In this paper, we present a wormhole-switched NoC with virtual channels for high dependability systems hardened against soft errors. The NoC is developed based on results of a Failure Mode and Effects Analysis. It efficiently handles errors in different network layers and operates with formal guarantees. Our experimental evaluation, including an industrial avionics use case, shows that the network is able to achieve predictable behavior even in aggressive environments with very high error rates while presenting competitive overheads.Publicationtype: Journal Article90 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , Code-inherent traffic shaping for hard real-time systems(Association for Computing Machinery (ACM), 2019-10); ; © 2019 Association for Computing Machinery. Modern hard real-time systems evolved from isolated single-core architectures to complex multi-core architectures which are often connected in a distributed manner. With the increasing influence of interconnections in hard real-time systems, the access behavior to shared resources of single tasks or cores becomes a crucial factor for the system's overall worst-case timing properties. Traffic shaping is a powerful technique to decrease contention in a network and deliver guarantees on network streams. In this paper we present a novel approach to automatically integrate a traffic shaping behavior into the code of a program for different traffic shaping profiles while being as least invasive as possible. As this approach is solely depending on modifying programs on a code-level, it does not rely on any additional hardware or operating system-based functions. We show how different traffic shaping profiles can be implemented into programs using a greedy heuristic and an evolutionary algorithm, as well as their influences on the modified programs. It is demonstrated that the presented approaches can be used to decrease worst-case execution times in multi-core systems and lower buffer requirements in distributed systems.Publicationtype: Journal ArticleScopus© Citations 3 330 472 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , On Analyzing Memory Latency for Embedded CPS Platforms(2019-08)The current trend towards automation and connectivity is driving the increased adoption of complex and parallel computational embedded multiprocessors platforms in CPS. These platforms are characterized by a tightly-coupled shared memory system. Data storage and access have then a significant impact on performance and need to be carefully considered to comply with stringent timing constraints often required by CPS. However, verifying such timing requirements becomes more and more challenging due to the increasing complexity of the underlying memory system thereby leading to non-deterministic access latencies. In this paper we present some of the features that need to be considered when bounding shared memory latency in complex systems and discuss how standard system performance analysis methods can be enhanced to consider specific shared-memory hardware and software features like address mapping, locality of accesses and requests interleaving.Publicationtype: Conference Paper81 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Exploiting Locality for the Performance Analysis of Shared Memory Systems in MPSoCsThe integration trend and increased required computing power is driving the advent of common embedded consumer devices like MPSoCs platforms in the safety critical domain. MPSoCs often feature a shared tightly-coupled memory system where a careful management of data storage and transfers is a key enabler for performance. However, providing real-time guarantees for these platforms is extremely challenging as they rely on exploiting data locality to improve average latencies in shared-memory architectures. This effect is often disregarded by existing real-time analysis approaches which furthermore often focus solely on a single component of the memory system. In this paper, we propose a framework for the timing analysis of shared memory systems composed of on-chip scratchpad memories, off-chip DRAMs and DMA engines. The analysis captures the effect on the performance of the system of the locality of accesses, their interleaving and granularity.Publicationtype: Conference Paper188 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Special session: Future automotive systems design: Research challenges and opportunities(2018-10); ; ; ; Automotive systems are currently undergoing a radical shift in the way they are designed, implemented and deployed. Such changes impose an increased complexity and a high number of requirements in order to be more automated, connected, dependable and cost-effective. This raises several challenges that the embedded systems community has to face, encountered at different stages of systems development from modeling and design to software/hardware deployment and validation. This paper discusses current industrial trends and open problems in the hardware and software design of automotive systems, dictating rigorous constraints in terms of safety, real-time capabilities and security which have to be considered in future automotive systems design.Publicationtype: Conference Paper17 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , Compiler-based extraction of event arrival functions for real-time systems analysis(Schloss Dagstuhl - Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing, 2018-07); ; Event arrival functions are commonly required in real-time systems analysis. Yet, event arrival functions are often either modeled based on specifications or generated by using potentially unsafe captured traces. To overcome this shortcoming, we present a compiler-based approach to safely extract event arrival functions. The extraction takes place at the code-level considering a complete coverage of all possible paths in the program and resulting in a cycle accurate event arrival curve. In order to reduce the runtime overhead of the proposed algorithm, we extend our approach with an adjustable level of granularity always providing a safe approximation of the tightest possible event arrival curve. In an evaluation, we demonstrate that the required extraction time can be heavily reduced while maintaining a high precision.Publicationtype: Conference PaperScopus© Citations 6 227 177 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Prediction of abnormal temporal behavior in real-time systems(Association for Computing Machinery (ACM), 2018-04-09); ; ; ; Ensuring security in real-time and safety-critical systems is becoming extremely challenging, in particular due to the increasingly connectivity of these systems, such as in emerging autonomous vehicles that are subject to new and higher number of security attacks. The main characteristics of real-time systems is that they have strict timing constraints. These constraints must be met in order to ensure the correctness of the system. In this paper, we use the temporal properties derived from the timing analysis of the system required for safety, in order to detect the misbehavior of the system and improve its corresponding security features. For this, we define temporal boundaries which are used to detect the temporal off-nominal behavior of running applications. Moreover, we present a prediction scheme which uses the designated configuration in real-time systems.Publicationtype: Conference Paper157 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , On the benefits of multicores for real-time systemsIn real-time and safety-critical systems, the move towards multicores is becoming unavoidable in order to keep pace with the increasing required processing power and to meet the high integration trend while maintaining a reasonable power consumption. However, the benefit expected from multicore platforms may not step up to the mark, and real-time constraints can be easily violated. Indeed, an efficient use of multicore platforms usually requires a suitable parallelization of the software and a proper knowledge of the hardware constraints in order to find the best trade-off between increasing the parallelization benefit and decreasing contentions from accessing shared resources. In this paper, we illustrate this duality and investigate a general approach to automate some deployment decisions in order to maximize the benefit from using multicores while meeting the schedulability constraints of the system.Publicationtype: Conference Paper108