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    Item type:Publication, Access status: without files ,
    Programmable memristor emulator ASIC for biologically inspired memristive learning
    (2016-11-28)
    Ranjan, Rajeev
    ;
    Mendoza Ponce, Pablo Daniel
    ;
    Kankuppe, Anirudh
    ;
    John, Bibin
    ;
    Abu Saleh, Lait
    This paper details a fully programmable floating memristor (resistor with memory) emulator ASIC designed for biologically inspired memristive learning. Since real memristor is not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has a memristor emulator with conductance range from 4.88nS to 4.99μS (200KΩ to 204.8MΩ). The memristor emulator is a switchedresistor based circuit with processing performed off-chip in a FPGA. The processing has been planned to be off-chip to get the freedom of programmability of any function. This paper explains the memristor emulator and the realization of synapse functionality used in neuromorphic circuits like long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has been designed and fabricated in AMS 350nm process.
    Publicationtype: Conference Paper
      67
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    Item type:Publication, Access status: without files ,
    Integrated circuit with memristor emulator array and neuron circuits for neuromorphic pattern recognition
    (IEEE, 2016)
    Ranjan, Rajeev
    ;
    Kyrmanidis, Alexandros
    ;
    Hellweg, Wolf Lukas
    ;
    Mendoza Ponce, Pablo
    ;
    Abu Saleh, Lait
    This paper details an array of switch resistor based memristor emulators with integrate & fire based neuron ASIC for the development of memristor based pattern recognition. The designed ASIC has 4 memristor emulators with a conductance range from 195 nS to 190 uS; processing has been planned to be off-chip to get the freedom of programmability of any function in ASIC. The ASIC has 2 integrate and fire (I & F) neuron circuits which are planned to be used in conjunction with memristors in a large multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neurons and an algorithm of pattern recognition simulated in Ltspice. The ASIC has been fabricated in AMS 350nm process.
    Publicationtype: Conference Paper
      13