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    Item type:Publication, Access status: without files ,
    Software-level TMR approach for on-board data processing in space applications
    (IEEE, 2018-07-11)
    Janson, Karl
    ;
    Treudler, Carl Johann
    ;
    Hollstein, Thomas
    ;
    Raik, Jaan
    ;
    Jenihhin, Maksim
    Handling faults in computing systems is often expensive in terms of power, area and financial costs. In domains requiring high reliability in harsh environments, like the space domain, special highly reliable components are used, which may adversely impact the processing performance. In this paper, we propose the STROBES algorithm for fault handling in a multi-node embedded system which can be composed of standard commercial off-the-shelf components. In particular, it does not require underlying synchronization, but relies on embedded system's properties to derive bounds for communication and processing times. The algorithm can handle asynchronous behavior between the nodes up to user-defined bounds, in addition to a fault in the state or fail-stop failure of a single node. Theoretical analysis shows that this is sufficient for extended operating times. Experimental data show the efficient behavior of the STROBES algorithm for practical application with different state and time bounds.
    Publicationtype: Conference Paper
      118
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    Item type:Publication, Access status: without files ,
    Augmenting all solution SAT solving for circuits with structural information
    (IEEE, 2018-07-11)
    Tibebu, Abraham Temesgen
    ;
    Fey, Görschwin
    All solutions SAT (All-SAT) is important in applications where we require enumerating all satisfying assignments of a propositional formula, e.g., when reasoning over many or all possible test patterns in Automatic Test Pattern Generation (ATPG). We applied structural analysis starting from primary inputs or primary outputs to generalize a current total assignment to a partial assignment. This speeds up the determination of all satisfying assignments. The experiments were conducted using a large number of random instances and different available All-SAT solvers. We show that structural analysis techniques can significantly speed up enumeration of all satisfying assignments of combinational circuits and yield the the second largest number of total satisfying assignments from all compared All-SAT solvers.
    Publicationtype: Conference Paper
      257