3 results
Now showing1 - 3 of 3
- Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , Radiation-tolerant all-digital PLL/CDR with varactorless LC DCO in 65 nm CMOS(Multidisciplinary Digital Publishing Institute (MDPI), 2021-11-10); ; ; ; This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5MeVcm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40MHz to 320MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11mW and an FOM of −235 dB.Publicationtype: Journal ArticleScopus© Citations 6 113 691 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , Single-event effect responses of integrated panar inductors in 65 nm CMOS(IEEE, 2021-10-18); ; ; ; This article describes a previously unreported single-event radiation effect in spiral inductors manufactured in a commercial CMOS technology when subjected to ionizing radiation. Inductors play a major role as the component determining the frequency of LC tank oscillators, which is why any radiation effects in these passive components can have detrimental impact on the performance of clock generation circuits. Different experiments performed to localize and characterize the Single-Event Effect (SEE) response in a radiation-hardened PLL circuit are discussed and presented together with an hypothesis for the underlying physical mechanism.Publicationtype: Journal ArticleScopus© Citations 9 84 187 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Methods for clock signal characterization using FPGA resourcesReliable measurement of clock signal parameters is an important tool for calibration and validation of circuits used in precise-timing applications. Such parameters include frequency, phase, duty cycle and channel-to-channel skew. Especially in applications in which testing time for multiple channels is a significant factor, efficient parallelization of measurements is crucial, often coming with significant extra cost. We present a technique for characterization of clock signal parameters using off-the-shelf (FPGA) evaluation hardware. Two methods for both static measurements (steady-state behaviour) as well as dynamic measurements are presented. For the two measurement methods proposed, case studies are presented and their performance discussed.Publicationtype: Journal Article196