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    Item type:Publication, Access status: without files ,
    Hardware-accelerated Compression Core on RISC-V for Online-BCG Data Reduction
    (2024-10)
    Rahman, Kazi Mohammad Abidur
    ;
    Ahmed, Abdelrahman Noshy Abdelalim
    ;
    Fey, Görschwin
    ;
    Kulau, Ulf
    Efficient compression of Ballistocardiography (BCG) data is critical for wearable and Ultra-Low-Power (ULP) applications, particularly in space-bound missions. This paper presents a hardware accelerator for data compression integrated into a NEORV32 RISC-V system specifically designed to enhance the performance of BCG sensors in resource-constraint environments. Utilizing hardware-accelerated Modified-Delta encoding with a software-based simple bit-packing compression can significantly improve real-time data transmission and storage efficiency. Implemented on the Lattice iCE40UP5K FPGA, the proposed method can achieve up to 13× speed improvement over traditional software solutions while maintaining a minimal footprint of 3719 Look-Up Tables (LUTs). This technique paves the way for ultra-efficient, wearable BCG sensors, which are crucial for, e.g. deep-space missions where energy and storage are at a premium.
    Publicationtype: Conference Paper
      15
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    Item type:Publication, Access status: without files ,
    Efficient Online Compression for MEMS based BCG Wearable Sensors on ULP FPGA
    (2023)
    Kulau, Ulf
    ;
    Ahmed, Abdelrahman Noshy Abdelalim
    Compression of Ballistocardiography (BCG) data is of a great importance specially in the context of wearables and ultra-low power (ULP) applications, respectively. This paper presents an efficient and yet simple compression core for BCG data that can be integrated to MEMS sensor or on ULP FPGAs. The proposed compression technique is a modified delta encoding algorithm that can compress data efficiently ranging from lossless to lossy compression, while the design was derived from BCG specific requirements. The technique offers flexibility with respect to compression performance and signal distortion where compression ratio can be traded for lossless compression and vice verse. Evaluations of 4 BCG data sets show an average compression ratio of 3 with adequate PRDN. This compression core is further implemented in VHDL and it utilizes 234 LUTs of FPGA resources supporting online compression.
    Publicationtype: Conference Paper
      48