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    Item type:Publication, Access status: without files ,
    FPGA-specific optimizations by partial function evaluation
    (IEEE, 2011-06)
    Manteuffel, Henning
    ;
    Başsoy, Cem Savaş
    ;
    Mayer-Lindenberg, Georg Friedrich
    Partial evaluation is a common optimization technique in compiler design. It is also used in hardware synthesis for simplifying modules with constant signals. In this paper we introduce a new evaluation method for imperative programs in high-level synthesis, which benefits from control data, whose values do not vary in different program executions and are thus determinable in advance. The key aspect is to collect intermediate-results during evaluation which are then used for hardware-specific optimizations, such as constant folding, reduction of data-widths or elimination and parallelization of memory accesses. In case of memory intensive applications we are able to reduce the runtime of up to 20%.
    Publicationtype: Conference Paper
      21
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    Architecture of a pipelined datapath coarse-grain reconfigurable coprocessor array
    (IEEE, 2007)
    Hanoun, Abdulrahman
    ;
    Manteuffel, Henning
    ;
    Mayer-Lindenberg, Fritz
    ;
    Galjan, Wjatscheslaw
    In this paper, we present the architecture of a coarse-grain reconfigurable cell designed for pipelined arithmetic computing applications. We apply the concept of separation between control-path and computation-path logic in the so-called reconfigurable coprocessor array architecture. Variations of the cells are implemented on CMOS 0.35 and 0.13 technologies and subjected to a group of benchmarks. The resulting delay area products showed that dual-ALU cells have about 50% smaller area-delay product than the single-ALU cell has.
    Publicationtype: Conference Paper
      8