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Item type:Publication, Access status: with files , High-Level FPGA-Programmierung mit automatisch generierten Netzwerken von AutomatenDue to the increasing number of gates and the integration of hard-wired elements within Field Programmable Gate Arrays (FPGAs), high-level language programmability and tools become more necessary. In this thesis the TransC language is introduced in which programs are coded as networks of finite state machines. Concepts for concurrency,interprocess communication and synchronization are developed and optimization techniques are described. Furthermore, a compiler is implemented that generates efficient VHDL code.Publicationtype: Doctoral Thesis796 1358 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , FPGA-specific optimizations by partial function evaluationPartial evaluation is a common optimization technique in compiler design. It is also used in hardware synthesis for simplifying modules with constant signals. In this paper we introduce a new evaluation method for imperative programs in high-level synthesis, which benefits from control data, whose values do not vary in different program executions and are thus determinable in advance. The key aspect is to collect intermediate-results during evaluation which are then used for hardware-specific optimizations, such as constant folding, reduction of data-widths or elimination and parallelization of memory accesses. In case of memory intensive applications we are able to reduce the runtime of up to 20%.Publicationtype: Conference Paper21 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Architecture of a pipelined datapath coarse-grain reconfigurable coprocessor array(IEEE, 2007); ; In this paper, we present the architecture of a coarse-grain reconfigurable cell designed for pipelined arithmetic computing applications. We apply the concept of separation between control-path and computation-path logic in the so-called reconfigurable coprocessor array architecture. Variations of the cells are implemented on CMOS 0.35 and 0.13 technologies and subjected to a group of benchmarks. The resulting delay area products showed that dual-ALU cells have about 50% smaller area-delay product than the single-ALU cell has.Publicationtype: Conference Paper8