10 results
Now showing1 - 10 of 10
- Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , An impedance spectroscopy ASIC for low-frequency characterization of biological samplesThis paper describes the design and testing of an ASIC for impedance spectroscopy of biological samples at frequencies up to 40 kHz. The circuit is designed in the 350 nm AMS H35B4 technology and enables the measurement of impedances in the range of 10 kW up to 28 MW. The design features a digital oscillator and a current-to-voltage converter. The ASIC is used to monitor the growth of yeast cell cultures and porcine chondrocytes, in real-time, using a standard 384-well plate and copper electrodes.Publicationtype: Conference PaperScopus© Citations 1 186 242 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Array test structures for gate dielectric integrity measurements and statistics(IEEE, 2012-05-11); ; ; An array test structure for highly parallelized stressing and measurements of ultrathin MOS gate dielectrics is presented. The array test structure consisting of thousands of NMOS devices under test (DUTs) provides a large and significant statistical base for analysis of dielectric breakdown and the stress induced degradation of transistor parameters. The test array has been fabricated in a standard mixed-mode 130 nm CMOS technology. As such technologies offer both thin and thick gate dielectrics for MOS transistors, different gate dielectric thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages and prevent the control logic from degradation.Publicationtype: Journal Article11 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A configurable integrated circuit for biomedical signal acquisition(Springer, 2011-01); ; ; ; Publicationtype: Conference Paper33 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , An integrated multi-channel system for biomedical signal acquisition(SciTePress, 2011); ; ; ; A CMOS configurable system-on-chip (SoC) for biomedical signal acquisition is described. The SoC is composed of 10 channels, each channel including a programmable analog front-end (AFE) and a 20 bit analog-to-digital converter (ADC). The digitized signals are read out via a high-speed serial communication bus. The AFE includes a common-mode rejection ratio (CMRR) calibration circuitry resulting in a CMRR of more than 80 dB and an active DC-suppression circuitry giving the DC-coupled instrumentation amplifier the possibility to tolerate DC-offsets of up to ± 1 V for a power supply voltage of 3.3 V. In low-noise mode the AFE achieves an input referred noise of less than 50 nVrms for EEG application (0.5-70 Hz) and the power consumption of a channel including AFE and ADC is less than 5 mW in low-power mode. A prototype has been fabricated in a 0.35 μm CMOS process.Publicationtype: Conference Paper22 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Reliability analysis of gate dielectrics by applying array test structures and automated test systems(IEEE, 2009-11); ; ; In this paper, we present an approach to analyse the degradation behaviour of the gate dielectric of thousands of MOS transistors simultaneously. Our approach is based on array test structures and automated test systems. The array test structures with a matrix-like arrangement of the MOS devices under test (DUT) have been designed and fabricated in a 130 nm mixed-mode CMOS process. They permit to stress up to 4k DUTs under same conditions. Several array test structures with different perimeters as well as areas integrated on one chip are available. Low-cost automated test systems allow for gate voltage stress experiments on a large scale with numerous array test structures in parallel. Experimental results are shown.Publicationtype: Conference Paper7 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Array test structure for ultra-thin gate oxide degradation issuesAn array test structure for highly parallelized measurements of ultra-thin MOS gate oxide failures caused by degradation is presented. The test structure allows for voltage stress tests of several thousand NMOS devices under test (DUTs) in parallel to provide a large and significant statistical base regarding soft as well as hard breakdown and stress induced degradation of transistor parameters. The array has been fabricated in a standard 130 nm CMOS technology. As mixed mode technologies provide both thin and thick oxide MOS transistors, different gate oxide thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages.Publicationtype: Conference Paper7 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Highly sensitive biomedical amplifier with cmrr calibration and dc-offset compensationTo cover a wide range of biomedical applications, the presented instrumentational amplifier (INA) for acquisition of biomedical signals is adjustable regarding power consumption and noise. In addition, DC-offsets larger than & 500 mV resulting from electrochemical potentials of the electrodes can be compensated by applying a voltage to an additional input. To achieve a high common mode rejection ratio (CMRR) of more than 80 dB, a digitally controlled calibration circuitry has been integrated. The novel concept of calibrating the CMRR in the high resistive feedback loop of an opamp and the DC electrode potential suppression does not require any external components. The INA has been fabricated in a 350 nm CMOS technology.Publicationtype: Conference Paper13 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Analog circuit calibration with single poly non-volatile memories(IEEE, 2008-11); ; ; A single poly non-volatile memory module for analog circuit calibration fabricated in a standard 350 nm CMOS process is presented. This module performs the read, program and verify operations for non-volatile storage applications. This circuitry can be used, e.g. for storing data to individually adjust sensitive device parameters of biomedical analog front ends to meet precisely the target specifications. The module can be embedded in analog or mixed signal chips based on 350 nm CMOS technology.Publicationtype: Conference Paper6 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A 130nm CMOS programmable operational amplifierIn this work we present a programmable 1.2 V Operational Amplifier (OpAmp) realized in a standard 130 nm CMOS technology. The OpAmp is based on a 3 V rail-to-rail input/output topology. The experimental results show the feasibility of using higher voltage topologies in conjunction with multi-threshold (multi-Vth) process options for low voltage designs. The programming range extends from a low-noise to a low-power mode. In addition, a constant-gm stage has been added to the rail-to-rail input. In low-noise mode the OpAmp has a low input thermal noise voltage of 5.1 nV/√Hz and in lowpower mode a power consumption of only 203 μW. Over the whole programming range the OpAmp maintains unity-gain stability with its phase margin varying between 58° and 62°Publicationtype: Conference Paper15 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , Simultaneous large-scale reliability analysis of ultra-thin MOS gate dielectrics using an automated test system(Copernicus Publications, 2008-05-26); ; ; This article presents an automated test system targeting the large-scale analysis of ultra-thin MOS gate dielectric degradation. The system allows for stress tests at elevated temperatures as well as supply voltages and long-term tests of thousands of MOS devices simultaneously. The aim is to build-up large and hence significant statistics about the degradation process as a function of time. © Author(s) 2008.Publicationtype: Journal Article251 239