4 results
Now showing1 - 4 of 4
- Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Realization of ultra-low power I/OThis paper summarizes the exploratory work conducted at IBM which seeks to reduce electrical I/O power consumption to facilitate both power distribution and device cooling for future exascale computing systems. The development of novel low-loss dielectric materials was coupled with design for performance to achieve low channel loss by minimizing reflections and energy dissipation due to non-ideal current return paths. A printed circuit board was fabricated and tested, with results confirming a 20% reduction of channel loss at 10GHz when compared to currently leading commercial materials. This 3dB improvement in loss for a 15dB channel, can offer a 50% I/O power reduction when used with power scalable driving/receiving circuits.Publicationtype: Conference Paper97 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Signal and power integrity (SPI) co-analysis for high-speed communication channels(Curran Associates, Inc., 2013-01); ; ; ; The modeling of multiple high-speed chip-to-chip communication links over first (IC package) and second (board) level interconnects is addressed in this paper for data rates up to 28 Gb/s with model-to-hardware correlation. The suggested methodology is based on a bottom-up hybrid approach combining semi-analytical and numerical models, which are able to simultaneously consider the signal and power integrity domains and allow the incorporation of power noise models for the time domain link simulation. The required model complexity and the design space for passive interconnects are explored by analyzing diverse via and channel configurations.Publicationtype: Conference Paper174 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Electrical performance of a multiport interposer for measurements of dense via arraysIn this paper the bandwidth limitations of two types of multiport probing fixtures for measurements of high density via array structures are investigated. Using a two-tier calibration technique and custom-made calibration substrates, error parameters for the probing fixtures were extracted and used to evaluate variability in measurements and substrate correction parameters. Results show adequate repeatability of the obtained error parameters up to 20 GHz. Digital links were measured utilizing these probing fixtures and results were compared to S-parameter measurements using RF microprobes. Good correlation up to 10 GHz - 15 GHz was established when compared to microprobe based measurements of link structures with stub access vias. For link structures with through access vias the adequate correlation bandwidth was founded to be 5 GHz - 10 GHz.Publicationtype: Conference Paper12 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Novel multiport probing fixture for high frequency measurements in dense via arraysIn this paper the authors present a novel multiport probing fixture for high frequency measurements of dense via arrays. The probing fixture consists of a 36 mm by 36 mm multilayer printed circuit board plugged into an LGA socket clamped down to the device under test using custom hardware. The test signal is launched from top surface mounted coaxial connectors and fanned in with striplines to a 1 mm via pitch on the bottom side. Custom calibration substrates are used to deembed the probing fixture from measurements by applying multiport deembedding techniques. The effect of contact pressure on obtaining reproducible measurements is investigated.Publicationtype: Conference Paper20