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Item type:Publication, Access status: without files , Effect of experimental factors on the properties of PEDOT-NaPSS galvanostatically deposited from an aqueous micellar media for invasive electrodes(IEEE, 2012-12); ; ; Poly(3,4-ethylenedioxythiophene) (PEDOT) coat for invasive electrodes has been generated considerable interest in terms of electrical properties and biocompatibility. Adequate formulations and methodology are necessary to deposit polymer reproducibly on macro and micro-electrodes. Electrochemical properties of PEDOT as interface material were assessed with respect to different experimental factors. PEDOT/NaPSS was polymerized from a sodium polystyrenesulfonate (NaPSS) dispersion. The dispersion was characterized by cyclic voltammetry and its critical micellar concentration (CMC) value is reported, according to our best knowledge, for the first time for PEDOT deposition. The polymer obtained was studied using Raman spectroscopy, impedance and cyclic voltammetry measurement. PEDOT-NaPSS coat shows high charge injection (Qinj), low interfacial impedance (Z) and superficial chemical stability (Raman). This study provides a simple, constant and reproducible framework to coat invasive electrodes.Publicationtype: Conference Paper10 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Array test structures for gate dielectric integrity measurements and statistics(IEEE, 2012-05-11); ; ; An array test structure for highly parallelized stressing and measurements of ultrathin MOS gate dielectrics is presented. The array test structure consisting of thousands of NMOS devices under test (DUTs) provides a large and significant statistical base for analysis of dielectric breakdown and the stress induced degradation of transistor parameters. The test array has been fabricated in a standard mixed-mode 130 nm CMOS technology. As such technologies offer both thin and thick gate dielectrics for MOS transistors, different gate dielectric thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages and prevent the control logic from degradation.Publicationtype: Journal Article11 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Toward the optimal architecture of an ASIC for neurostimulation(SciTePress, 2012); ; ; Electrical Neurostimulation has been effective in several medical therapies and also for restoring physiological, sensory and neuromuscular deficits. The rectangular pulse waveform has been used as a standard shape for neural stimulation. However, it has been shown that non-rectangular waveforms provide a more energy-efficient neural stimulation. An ASIC has been developed composed of a stimulator, capable of driving several current waveforms, and an analog channel for biosignal acquisition. The design is implemented in 130 nm / 1.2 V CMOS technology, requiring a silicon area of 0.696 mm 2. Experimental results show that the stimulator can generate analog signals from a digital input of 8 bits. The output stage can drive up to ±9.8 μA, with a DNL and INL of 0.47 and 1.05 LSB, respectively. Its SFDR is 50.2 dB. And it consumes a maximum of 128.12 μW. The analog input channel presents a power consumption of 140 μW, a gain of 52.2 dB, a bandwidth of 0.5 - 1130 Hz and 10 μV rms of noise.Publicationtype: Conference Paper10 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A configurable integrated circuit for biomedical signal acquisition(Springer, 2011-01); ; ; ; Publicationtype: Conference Paper33 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Understanding the mechanisms of degradation and failure observed in ESD protection devices under system-level tests(2010-06-01); The behavior and the failure mechanism of a monolithic bidirectional ESD protection device under a system-level ESD pulse are investigated. The device is realized by two diffused vertical back-to-back connected diodes. When the bottom p-n junction is stressed with an 18-kV system-level pulse, the device exhibited the typical signature of second thermal breakdown. Surprisingly, no ESD damage could initially be observed by measuring the poststress leakage current, even when the ESD level was further increased to 30 kV. A degrading $IV$ behavior was later found to be associated with the second thermal breakdown. Based on simulations, local crystal defects are proposed to explain the observed degradation of the $IV$ behavior. It is shown that, in this case, leakage-current measurements alone fail to detect such ESD damage. Failure analysis of the device confirms the existence of the crystal damage.Publicationtype: Journal Article12 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Design and implementation of an integrated RF system-in-package for healthcare applicationsA 3 channel ECG system with wireless data transmission is presented. It is built as a System in Package (SiP) consisting of 6 dies and 39 SMD components mounted on a FR4 substrate at a size of 2.45 x 2.45 mm2. Design considerations and ASIC partitioning is addressed in this work. In addition, measurement results are presented proving that a SiP can compete with a System on Chip.Publicationtype: Conference Paper9 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Improved impact-ionization modelling and validation with pn-junction diodesImpact-ionization at low and high electric field as well as the temperature dependence has to be modeled well in order to improve the predictive capability of TCAD tools. The high field behavior is of particular interest for ESD protection devices with low breakdown voltages which are used to protect ICs made with modern technologies. In this paper, the model for estimating the impact-ionization proposed by Valdinoci [1] with the parameters of Reggiani [2] has been examined with diodes of various breakdown voltages. It was found that the experimental breakdown voltages of the diodes are underestimated using that model. The cause was traced back to the overestimation of the electron impact-ionization coefficient at high electric fields. By adjusting the model parameters to the experiments of Van Overstraeten [3] and Grant [4], who measured the impact-ionization coefficient in silicon for fields up to 7.7 × 105 V/cm, we extend the model's validity to high fields. With the new parameter set, a much better agreement to the measured breakdown voltages is obtained. As a check for the temperature dependence of the impact-ionization, the diodes were further investigated under 100 ns transmission line pulses (TLP). The measured highcurrent I-V characteristic is well reproduced by simulations using the new model, as opposed to the well-established model based on Chynoweth's law. Both the failure level and the damage location are well predicted by the simulation.Publicationtype: Conference Paper12 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Reliability analysis of gate dielectrics by applying array test structures and automated test systems(IEEE, 2009-11); ; ; In this paper, we present an approach to analyse the degradation behaviour of the gate dielectric of thousands of MOS transistors simultaneously. Our approach is based on array test structures and automated test systems. The array test structures with a matrix-like arrangement of the MOS devices under test (DUT) have been designed and fabricated in a 130 nm mixed-mode CMOS process. They permit to stress up to 4k DUTs under same conditions. Several array test structures with different perimeters as well as areas integrated on one chip are available. Low-cost automated test systems allow for gate voltage stress experiments on a large scale with numerous array test structures in parallel. Experimental results are shown.Publicationtype: Conference Paper7 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Array test structure for ultra-thin gate oxide degradation issuesAn array test structure for highly parallelized measurements of ultra-thin MOS gate oxide failures caused by degradation is presented. The test structure allows for voltage stress tests of several thousand NMOS devices under test (DUTs) in parallel to provide a large and significant statistical base regarding soft as well as hard breakdown and stress induced degradation of transistor parameters. The array has been fabricated in a standard 130 nm CMOS technology. As mixed mode technologies provide both thin and thick oxide MOS transistors, different gate oxide thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages.Publicationtype: Conference Paper7 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , 12-bit hybrid C2C DAC based SARADC with floating voltage shield(IEEE, 2009); ; ; Neubauer, HaraldA successive approximation ADC based on the C2C DAC architecture is introduced. The ADC designed in a 0.18μm CMOS 2 Poly 4 Metal process uses a hybrid capacitive DAC combining the best of the binary weighted capacitive array and the C2C array. C2C ladder based architectures are very attractive for implementation because of its small area, high speed and low power consumption. However a major drawback associated with this DAC is the presence of high parasitic bottom plate capacitances. A concept called the floating voltage shield (FVS) is introduced to reduce the effect of these parasitic capacitances and maximize the effective use of the C2C DAC features. The converter consists of the hybrid DAC, a two stage preamplifier followed by a dynamic latch, switch array and digital circuitry for switching and control. The ADC consumes a maximum power of 630μW at a peak conversion rate of approximately 2MS/s from a 1.8V supply voltage and 40MHz clock. Use of extremely simple and yet robust analog architectures for the comparator make the ADC operation less prone to process variation errors.Publicationtype: Conference Paper18