13 results
Filters
Settings
Now showing1 - 10 of 13
- Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A high-linearity high-stability dynamic amplifierThis brief presents an open-loop Gm-C dynamic amplifier with a high linearity and a high temperature and supply voltage stability. The main part of the amplifier employs two asymmetric differential pairs to enhance the transconductance linearity. The amplifier maintains a nearly constant gain of 23.29 dB within a differential input range of −40 to + 40 mV, and achieves a total harmonic distortion (THD) of −70.42 dB. Both the THD and voltage gain are better than other open-loop linear amplifiers, demonstrating that the proposed circuit offers an improved linearity and amplification capability. In addition, its input-referred noise (IRN) is 2.46 nV/ √Hz, lower than that of similar linear amplifiers. The biasing circuit of the amplifier adopts a constant-gm biasing circuit, which improves the temperature and supply voltage stability of the amplifier transconductance and voltage gain. When the differential input is 1 mV, the power supply voltage variation is ±10% around 5 V, and the temperature variation is −40 to + 120 + C, the standard deviation of voltage gain is 0.25093, and the range of voltage gain is from 13.99 to 15.05 times, indicating a better stability compared to the traditional Gm-C amplifiers.Publicationtype: Journal Article11 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A Low-Power 2nd-Order ΔΣ Modulator with a Single Current-Starving FIAThis brief presents a compact single-loop discretetime (DT) modulator. The design introduces a dual-phase 2nd-order integrator with a single current-starving floating inverter amplifier (CS-FIA). The charge dissipation and operating point shift during dynamic operation are reduced, as the FIA operates in a relatively stable subthreshold region throughout the entire clock cycle. This enables improved power efficiency across a wide supply voltage range. The ΔΣ modulator is fabricated in a 180 nm CMOS process. It achieves 102.4 dB SNDR at 256 kHz sampling frequency. With a 1.4 V supply, the circuit consumes 8.23 μW, leading to a state-of-the-art Schreier FoM of 183.2 dB. Across a supply voltage range of 1.2 V to 1.6 V, the modulator continuously maintains a FoM above 182 dB.Publicationtype: Journal Article34 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A highly integrated analog front-end combining level shifter, programmable gain amplifier, and low-pass filter for automotive BMSThis brief presents a highly integrated analog front-end (AFE) for automotive battery management systems (BMS). The proposed AFE combines level shifter (LS), programmable gain amplifier (PGA), and low-pass filter (LPF) functions into a single switched-capacitor architecture. Additionally, an offset cancellation scheme is employed to cancel the amplifier offset. Designed in a 130 nm BCD process, the proposed circuit utilizes capacitively-coupled inputs along with high-voltage (HV) switches realized with 5 V MOS devices placed in isolated N-Buried layer (NBL) pockets to handle input voltages up to 100 V. The circuit simultaneously provides programmable gain from 1 to 5 times and first-order low-pass filtering with a 1.6 kHz cutoff frequency for anti-aliasing. This three-in-one integration significantly reduces component count, system complexity, and power consumption compared to traditional cascade approaches. Designed for 125 kS/s operation, the AFE enables high-precision cell voltage monitoring with over 16-bit effective number of bits (ENOB). Operating at a 5 V supply, the AFE consumes only 330μ A (not including the ADC), making it a highly efficient solution for electric vehicle BMS applications.Publicationtype: Journal Article31 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , A 10-b 5-GS/s passive T/H assisted time-interleaved pipelined-SAR ADC with pre-quantization and background offset calibrationThis letter presents a 10-bit 5-GS/s time-interleaved (TI) pipelined successive-approximation-register (SAR) analogue-to-digital converter (ADC). By utilizing a full-speed passive track-and-hold circuit (T/H), pre-quantization can be performed in parallel, alleviating the timing constraint in the first stage. The chopped switches in the passive T/H enable input-independent background offset calibration for comparators and residue amplifiers. Fabricated in a 28-nm CMOS process, the prototype ADC achieves 51.8-dB SNDR and 67.9-dB SFDR at the Nyquist input.Publicationtype: Journal Article37 21 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A fully integrated SPAD sensor with photoluminescent encapsulation and die-bonded μLEDs for implantable oxygen monitoringContinuous monitoring of oxygen concentration in biological tissue is critical for adaptive therapies and long-term implant diagnostics. This work presents a heterogeneously integrated photoluminescent oxygen sensing system combining CMOS single-photon avalanche diodes (SPADS) with pulse- and current-controllable micrometer-sized LEDs (μLEDs) die-bonded onto the chip. A single-step encapsulation using an optically active polymer integrates both the sensing and protecting layers. The system achieves a concentration resolution of 0.03 to 0.5 % O2 with an energy consumption of 73.4 nJ per measurement at up to 6.6 ksps, outperforming state-of-the-art systems by 3x in accuracy, 20x in sampling rate, and requiring only one-third of the power.Publicationtype: Conference Paper39 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A 500 MS/s Robust 2b/cycle Pipelined-SAR ADC Achieving 64.6-dB SNDR and 82.6-dB SFDR With Linearity Enhancement TechniquesThis letter presents a 14-bit 500-MS/s 3-stage pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC). By exploiting robust 2b/cycle SAR ADCs, this ADC incorporates significant voltage and time redundancy. High SFDR is achieved through several linearity enhancement techniques. First, a DAC splitting technique addresses the common-mode voltage matching problem between the input buffer and the sampling circuit. Second, a reference charge neutralization minimizes reference ripple. Finally, a digital harmonic correction is realized with a low-cost and low-latency LUT. Fabricated in a 28-nm CMOS process, the prototype ADC achieves 64.6-dB SNDR and 82.6-dB SFDR at Nyquist.Publicationtype: Journal Article59 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , An 8-Bit precision 10T SRAM compute-in-memory macro using ADC with small areaThis brief proposes a charge-domain analog Compute-In-Memory (CIM) architecture based on multi-bit SRAM. The proposed structure consists of a 64×64 10T1C SRAM array, which can perform 1024 MAC operations between 4-bit signed input and weight within a single clock cycle. An 8-bit Analog-to-Digital Converter (ADC) is employed for quantization, converting the analog Multiply-Accumulate (MAC) results into 8-bit digital signals for output. The ADC module adopts capacitor array multiplexing, pseudo-differential sampling with double-terminal flipping method and matching layout designing to save area. The proposed circuit is implemented in 28nm process which operates at a supply voltage of 0.8V. It achieves an energy efficiency of 184 TOPS/W and an area efficiency of 7.3 TOPS/mm², and reaches an accuracy of 86.9% in the training on CIFAR-10 dataset. When compared with other works, the highlight of this work is the highest energy efficiency and the highest area efficiency on 4-bit input and weight precision normalized to 28nm.Publicationtype: Journal Article91 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , A low-cost and low-latency inter-stage nonlinearity error calibration algorithm for pipelined ADCsPipelined analogue-to-digital converters suffer from inter-stage gain errors and inter-stage nonlinearity errors due to gain variations and nonlinearity in residue amplifiers. While a polynomial-based calibration algorithm can address these errors, its conventional implementation demands excessive hardware resources and power consumption. This letter introduces a novel calibration algorithm that combines precomputation with a lookup table, achieving improved hardware efficiency while maintaining calibration accuracy and reducing latency.Publicationtype: Letter to the Editor60 26 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Current regulated LED driver with fast switch-off behavior for integrated optoelectronic implantsThis paper presents a power, speed and area optimized mini-LED driver integrated in 180 nm CMOS HV process and capable of sinking up to 4mA current. It aims to cover various applications of optoelectronic implants with a single design. The current driver consists of a drain-regulated self-cascode current mirror. An additional carrier sweep-out circuit reduces the mini-LED voltage fall time down to 4.7 ns. The current can be digitally adjusted from 0.5 mA to 4 mA, depending on its use-case. The temperature-compensated current reference provides 0.01 mA with a temperature coefficient (TC) of 210 ppm/°C between -10 °C and 110 °C leading to a TC of 357 ppm/°C for the output current. The successfully performed measurements for circuit under pad constructs revealed a possible size reduction only limited by the dimensions of the on-die processed mini-LEDs of 0.1 mm x 0.2 mm.Publicationtype: Conference Paper59 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A chopping-free single-trim bandgap reference using amplifier with PTAT offsetThis article presents a chopping-free single-trim bandgap reference with an amplifier proportional-to absolute temperature (PTAT) offset. This amplifier PTAT offset is helpful for improving the BGR accuracy. Unlike the classic differential amplifiers, whose input-referred offset is usually non-PTAT, the proposed amplifier realizes a PTAT offset through controlling the current of a BJT-based structure. Similar to other PTAT error sources in a bandgap reference, this PTAT offset can be eliminated easily through a single room-temperature trim at the reference voltage. This makes the proposed circuit very simple and highly accurate, since it eliminates the need of complicated amplifier-offset cancellation techniques, such as chopping or autozeroing, that are usually used in prior single-trim bandgap reference circuits. It also eliminates the high-frequency ripple at the reference output, due to the no need of chopping. Besides the proposed structure, this article also presents a new technique to generate the amplifier bias current using only a tail resistor. Since a complicated biasing circuit is no longer needed, the proposed circuit is further simplified. Implemented in a 180-nm BCD process, the temperature coefficient (TC) is 3–8 ppm/◦C at −55 ◦C∼125 ◦C after a single trim at the room temperature, the output noise is only 1.5 µVrms at 0.1–10 Hz, the current consumption is 590 µA, and the active area is 0.55 mm2. According to the best of our knowledge, this is the first ever single-trim bandgap reference with no need of chopping or autozeroing.Publicationtype: Journal Article91