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Item type:Publication, Access status: without files , Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioningThere is a trend towards to dense integration of embedded systems for cost, weight, and power savings. Integration of multiple critical software functions in a single embedded platform requires domain partitioning. Groups of independent software functions exist in isolated domains to maintain individual functional correctness, even in presence of errors. Software solutions such as Real-Time Operating Systems (RTOS) with time and space partitioning are state-of-the-art segregation approaches. As an alternative to these existing solutions, we present a robust, reliable, and efficient architecture with segregation support for safety- and security-critical embedded systems. Our solution hosts different software functions on a platform with as few hardware components as possible: the System-on-a-Chip (SoC) approach. The proposed architecture instantiates multiple self-contained soft processor systems on a single chip. The architecture offers hardware-enforced segregation and is completely transparent to software applications. We demonstrate this aspect by running multiple segregated instances of unmodified off-the-shelf Linux systems from a shared memory device. Since our architecture targets reconfigurable platforms, it is also flexible and can be tailored to application-specific needs at design time. Segregation is achieved with a hierarchical connection of memory busses by secure bus bridges. The bridges perform caching, prefetching, and burst accesses to efficiently avoid temporal conflicts on shared resources. Hence, our secure bridges allow to use soft processors for critical designs. We implement several prototypes and evaluate them by using novel bus observers for characterization of bus-centric architectures. Finally, we show the effectiveness of our implemented optimizations.Publicationtype: Journal Article22 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAsDecimal floating point operations are important for applications that cannot tolerate errors from conversions between binaryand decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carry-propagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.Publicationtype: Journal Article422 373 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , An asynchronous bus bridge for partitioned multi-soc architectures on FPGAsRecent FPGA families exhibit a bandwidth gap that is inverse to the widely known memory bottleneck of hardwired platforms: Behaviorally described soft processors are comparatively slow whereas FPGAs offer high-throughput state-of-the-art memory attachments. We show that it is possible to take advantage of this bandwidth gap to host functionally partitioned safety- and security-critical software functions. Our proposed multisystem architecture instantiates multiple self-contained local systems on a reconfigurable platform that operates from a shared but partitioned memory. We benchmark and evaluate a novel asynchronous bus bridge and demonstrate that the asynchronous architecture is scalable both at run-time and during place-and-route.Publicationtype: Conference Paper110 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A multi-core FPGA-based SoC architecture with domain segregationNowadays, FPGAs are sufficiently large to host not only single soft-core CPUs but a whole Multi-Processor System-on-a-Chip (MPSoC). They follow the recent trend of chip-multiprocessing. Given the requirement for domain segregation in safety and security related applications, we propose an FPGA-based architecture that achieves segregation by secure bus bridges. According to the SoC-paradigm, we use a single shared memory controller to reduce external component count. We pay special attention to performance evaluation and avoidance of temporal conflicts. The architecture is evaluated by dedicated bus observers using simulation and hardware prototypes and is finally benchmarked by running multiple isolated off-the-shelf Linux systems. © 2012 IEEE.Publicationtype: Conference Paper25 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , FPGA implementations of radix-10 digit recurrence fixed-point and floating-point dividersIn this paper we present three different radix-10 digit recurrence division algorithms for FPGA architectures. The first one implements the simple shift-and-subtract algorithm, whereas the second and third implementations each perform digit recurrence algorithm with signed-digit redundant quotient alculation and carry-save representation of the residuals. However, the second divider computes the quotient digit using a ROM whereas the third divider uses a quotient digit decomposition and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA and implementation results are given.Publicationtype: Conference Paper28 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: with files , A decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier on a Virtex-5 FPGADecimal Floating Point operations are important for applications that cannot tolerate errors from conversionsbetween binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, wepresent a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is basedon BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipelinestages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unitfor IEEE 754-2008 decimal64 data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unitand migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accuratescalar product unit's latency even by a factor of five.Publicationtype: Journal ArticleScopus© Citations 4 219 373 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , An IEEE 754-2008 decimal parallel and pipelined FPGA floating-point multiplierDecimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, scientific, commercial, and financial applications. In this paper we present an IEEE 754-2008 compliant parallel decimal floating-point multiplier designed to exploit the features of Virtex-5 FPGAs. It is an extension to a previously published decimal fixed-point multiplier. The decimal floating-point multiplier implements early estimation of the shift-left amount and efficient decimal rounding. Additionally, it provides all required rounding modes, exception handling, overflow, and gradual underflow. Several pipeline stages can be added to increase throughput. Furthermore, different modifications are analyzed including shifting by means of hard-wired multipliers and delayed carry propagation adders.Publicationtype: Conference Paper37 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , A radix-10 digit recurrence division unit with a constant digit selection functionDecimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, scientific, commercial, and financial applications. In this work we present a radix-10 digit recurrence division algorithm that decomposes the quotient digits into three parts and requires only the computation of five and two times the divisor. Moreover, the divisor's multiples are selected without multiplexers and the digit selection functions are independent of the divisor's value and do not require a lookup table. The algorithm has been synthesized and verified on a Xilinx Virtex-5 FPGA and implementation results are given.Publicationtype: Conference Paper37 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Dynamically reconfigurable dataflow architecture for high-performance digital signal processingIn this paper a dataflow architecture is introduced that maps efficiently onto multi-FPGA platforms and is composed of communication channels which can be dynamically adapted to the dataflow of the algorithm. The reconfiguration of the topology can be accomplished within a single clock cycle while DSP operations are in progress. Finally, the programmability and scalability of the proposed architecture is demonstrated by a high-performance parallel FFT implementation.Publicationtype: Journal Article35 - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Access status: without files , Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on Multi-FPGA platformsPublicationtype: Doctoral Thesis44